Adds the Device Tree binding documentation that allows to describe the Video Input Interface found in Toshiba Visconti SoCs. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@xxxxxxxxxxxxx> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> --- Changelog v2: - no change Changelog v3: - no change Changelog v4: - fix style problems at the v3 patch - remove "index" member - update example Changelog v5: - no change Changelog v6: - add register definition of BUS-IF and MPU .../bindings/media/toshiba,visconti-viif.yaml | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml diff --git a/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml new file mode 100644 index 000000000..19ef4242e --- /dev/null +++ b/Documentation/devicetree/bindings/media/toshiba,visconti-viif.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/toshiba,visconti-viif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 SoC Video Input Interface Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> + +description: + Toshiba Visconti5 SoC Video Input Interface (VIIF) + receives MIPI CSI2 video stream, + processes the stream with embedded image signal processor (L1ISP, L2ISP), + then stores pictures to main memory. + +properties: + compatible: + const: toshiba,visconti-viif + + reg: + items: + - description: registers for capture control + - description: registers for CSI2 receiver control + - description: registers for bus interface unit control + - description: registers for Memory Protection Unit + + interrupts: + items: + - description: Sync Interrupt + - description: Status (Error) Interrupt + - description: CSI2 Receiver Interrupt + - description: L1ISP Interrupt + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Input port, single endpoint describing the CSI-2 transmitter. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: VIIF supports 2 or 4 data lines + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 1 + maximum: 4 + + clock-lanes: + description: VIIF supports 1 clock line + const: 0 + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + viif@1c000000 { + compatible = "toshiba,visconti-viif"; + reg = <0 0x1c000000 0 0x6000>, + <0 0x1c008000 0 0x400>, + <0 0x1c00E000 0 0x1000>, + <0 0x2417A000 0 0x1000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_in0: endpoint { + remote-endpoint = <&imx219_out0>; + bus-type = <4>; + data-lanes = <1 2>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; -- 2.25.1
