Hi, On 5/29/23 23:48, Andy Shevchenko wrote: > On Mon, May 29, 2023 at 1:39 PM Hans de Goede <hdegoede@xxxxxxxxxx> wrote: >> >> The ACPI code takes care of enabling/disabling the PMC clk(s) for >> the sensors as necessary based on the runtime-pm state of the sensor. >> >> But the GMIN code this replaces also set the clk-rate of the PMC clk >> to 19.2 MHz. At least on BYT devices the PMC clks may come up running >> at 25 MHz instead of the expected 19.2 MHz. >> >> Ensure the sensor clk also runs at the expected 19.2 MHz for sensors >> using v4l2-async probing by explicitly setting it to 19.2 MHz when >> enumerating sensors in atomisp_csi2_bridge.c. > > ... > >> + ret = clk_prepare_enable(clk); >> + if (!ret) >> + clk_disable_unprepare(clk); > > I'm wondering if _enable / _disable required. As the comment says the BIOS may have the clock enabled at boot, the hw won't allow changing the rate while the clk is enabled and the clk-framework won't allow calling clk_disable_unprepare(clk) without first calling clk_prepare_enable(). All the sound/soc/intel/boards/*.c files which are used on BYT / CHT do the same thing before setting the codec clk speed. Regards, Hans
