On 9/27/2022 10:55 AM, Tinghan Shen wrote:
The MT8195 SCP is a dual-core RISC-V MCU. Extend the yaml file to describe the 2nd core as a subnode of the boot core. The configuration register is shared by MT8195 SCP core 0 and core 1. The core 1 can retrieve the information of configuration registers from parent node.
I think the commit message would not convince people you put scp 1 as subnode of scp 0. Regards, Peng.
Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx> --- .../bindings/remoteproc/mtk,scp.yaml | 97 ++++++++++++++++++- 1 file changed, 92 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 786bed897916..c012265be4eb 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -75,6 +75,83 @@ properties: required: - mediatek,rpmsg-name+ '#address-cells':+ const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^scp-c[0-9]+@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address space + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are varied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,mt8195-scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + type: object + description: + This subnode represents the rpmsg device. The namesof the devices + are not important. The properties of this node are defined by the + individual bindings for the rpmsg devices. + + properties: + mediatek,rpmsg-name: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Contains the name for the rpmsg device. Used to match + the subnode to rpmsg device announced by SCP. + + required: + - mediatek,rpmsg-name + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -110,16 +187,26 @@ additionalProperties: falseexamples:- | - #include <dt-bindings/clock/mt8192-clk.h> - scp@10500000 { - compatible = "mediatek,mt8192-scp"; + compatible = "mediatek,mt8195-scp"; reg = <0x10500000 0x80000>, <0x10700000 0x8000>, <0x10720000 0xe0000>; reg-names = "sram", "cfg", "l1tcm"; - clocks = <&infracfg CLK_INFRA_SCPSYS>; - clock-names = "main"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x105a0000 0x105a0000 0x20000>; + + scp-c1@105a0000 { + compatible = "mediatek,mt8195-scp-core"; + reg = <0x105a0000 0x20000>; + reg-names = "sram"; + + cros-ec-rpmsg { + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + };cros-ec-rpmsg {mediatek,rpmsg-name = "cros-ec-rpmsg";
