Hi Laurent, Thank you for the patch. On Tue, Aug 30, 2022 at 12:32 AM Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Mon, Aug 01, 2022 at 10:47:15PM +0100, Lad Prabhakar wrote: > > Document the CSI-2 block which is part of CRU found in Renesas > > RZ/G2L SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > --- > > RFC v2 -> v1 > > * Fixed review comments pointed by Rob and Jacopo. > > > > RFC v1 -> RFC v2 > > * New patch > > --- > > .../bindings/media/renesas,rzg2l-csi2.yaml | 149 ++++++++++++++++++ > > 1 file changed, 149 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > new file mode 100644 > > index 000000000000..f82f88c096df > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > @@ -0,0 +1,149 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > + > > +description: > > + The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L > > + (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction > > + with the Image Processing module, which provides the video capture capabilities. > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > You can drop the oneOf and write > Agreed. > items: > - enum: > - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > - renesas,r9a07g054-csi2 # RZ/V2L > - const: renesas,rzg2l-csi2 > > > + - enum: > > + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > + - renesas,r9a07g054-csi2 # RZ/V2L > > + - const: renesas,rzg2l-csi2 > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + interrupt-names: > > + const: csi2_link > > If there's a single interrupt you can drop the name. > OK, I will drop it. Cheers, Prabhakar > > + > > + clocks: > > + items: > > + - description: Internal clock for connecting CRU and MIPI > > + - description: CRU Main clock > > + - description: CPU Register access clock > > + > > + clock-names: > > + items: > > + - const: sysclk > > + - const: vclk > > + - const: pclk > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + items: > > + - description: CRU_CMN_RSTB reset terminal > > + > > + reset-names: > > + const: cmn-rstb > > Same here. > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@xxxxxxxxxxxxxxxx> > > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: > > + Input port node, single endpoint describing the CSI-2 transmitter. > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + data-lanes: > > + minItems: 1 > > + maxItems: 4 > > + items: > > + maximum: 4 > > + > > + required: > > + - clock-lanes > > + - data-lanes > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Output port node, Image Processing block connected to the CSI-2 receiver. > > + > > + required: > > + - port@0 > > + - port@1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - power-domains > > + - resets > > + - reset-names > > + - ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/r9a07g044-cpg.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + csi20: csi2@10830400 { > > + compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; > > + reg = <0x10830400 0xfc00>; > > + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, > > + <&cpg CPG_MOD R9A07G044_CRU_VCLK>, > > + <&cpg CPG_MOD R9A07G044_CRU_PCLK>; > > + clock-names = "sysclk", "vclk", "pclk"; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G044_CRU_CMN_RSTB>; > > + reset-names = "cmn-rstb"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + csi2_in: endpoint { > > + clock-lanes = <0>; > > + data-lanes = <1 2>; > > + remote-endpoint = <&ov5645_ep>; > > + }; > > + }; > > + > > + port@1 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + reg = <1>; > > + > > + csi2cru: endpoint@0 { > > + reg = <0>; > > + remote-endpoint = <&crucsi2>; > > + }; > > + }; > > + }; > > + }; > > -- > Regards, > > Laurent Pinchart
