Hi Paul,
Thank you for the patch.
On Fri, Aug 26, 2022 at 08:28:02PM +0200, Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the A83T with a dedicated controller that
> covers both the protocol and D-PHY. It can be connected to the CSI
> interface as a V4L2 subdev through the fwnode graph.
>
> This is not done by default since connecting the bridge without a
> subdev attached to it will cause a failure on the CSI driver.
No urgency, but would it be possible to fix this so that the CSI-2
receiver can be connected to the CSI unconditionally in DT ? The
connection exists at the hardware level in the SoC, and should thus
exist here too, regardless of whether or not a sensor is connected.
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 82fdb04122ca..ecf9f3b2c0c0 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 {
> status = "disabled";
> };
>
> + mipi_csi2: csi@1cb1000 {
> + compatible = "allwinner,sun8i-a83t-mipi-csi2";
> + reg = <0x01cb1000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_MIPI_CSI>,
> + <&ccu CLK_CSI_MISC>;
> + clock-names = "bus", "mod", "mipi", "misc";
> + resets = <&ccu RST_BUS_CSI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_csi2_in: port@0 {
> + reg = <0>;
> + };
> +
> + mipi_csi2_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> hdmi: hdmi@1ee0000 {
> compatible = "allwinner,sun8i-a83t-dw-hdmi";
> reg = <0x01ee0000 0x10000>;
--
Regards,
Laurent Pinchart
