Hi Paul,
Thank you for the patch.
On Thu, Jul 28, 2022 at 10:05:05PM +0900, Paul Elder wrote:
> Add support for UYVY as an output format. The uv_swap bit in the
> MI_XTD_FORMAT_CTRL register that is used for the NV formats does not
> work for packed YUV formats. Thus, UYVY support is implemented via
> byte-swapping. This method clearly does not work for implementing
> support for YVYU and VYUY.
>
> Signed-off-by: Paul Elder <paul.elder@xxxxxxxxxxxxxxxx>
>
> ---
> Changes in v2:
> - s@uv@U/V@
> - SP has been kept (so, uh, *not* changed in v2)
>
> UYVY for the self path has not been tested because no device supports
> it. The rk3399 has a self path, but does not have the
> MI_OUTPUT_ALIGN_FORMAT register and thus does not support UYVY. The
> i.MX8MP does support UYVY, but does not have a self path.
> ---
> .../platform/rockchip/rkisp1/rkisp1-capture.c | 41 +++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> index 9fb4879e65fa..0d5e3373e1f5 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> @@ -97,6 +97,12 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .uv_swap = 0,
> + .yc_swap = 1,
> + .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> + .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YUV422P,
> .uv_swap = 0,
> @@ -231,6 +237,13 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
> .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
> .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> + }, {
> + .fourcc = V4L2_PIX_FMT_UYVY,
> + .uv_swap = 0,
> + .yc_swap = 1,
> + .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
> + .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> + .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YUV422P,
> .uv_swap = 0,
> @@ -464,6 +477,20 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
> rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
> }
>
> + /*
> + * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for
> + * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY.
> + * YVYU and VYUY cannot be supported with this method.
> + */
> + if (rkisp1->info->features & RKISP1_FEATURE_MI_OUTPUT_ALIGN) {
> + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
> + if (cap->pix.cfg->yc_swap)
> + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> + else
> + reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
> + }
I dislike read-modify-write sequences when the register isn't fully
initialized to a known value somewhere. This issue applies to other
registers too, so we could fix it globally on top.
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> +
> rkisp1_mi_config_ctrl(cap);
>
> reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
> @@ -505,6 +532,20 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
> }
>
> + /*
> + * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for
> + * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY.
> + * YVYU and VYUY cannot be supported with this method.
> + */
> + if (rkisp1->info->features & RKISP1_FEATURE_MI_OUTPUT_ALIGN) {
> + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
> + if (cap->pix.cfg->yc_swap)
> + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES;
> + else
> + reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES;
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
> + }
> +
> rkisp1_mi_config_ctrl(cap);
>
> mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
--
Regards,
Laurent Pinchart
