On Sat, 2010-07-31 at 09:55 -0400, Andy Walls wrote: > On Fri, 2010-07-30 at 15:45 +0300, Maxim Levitsky wrote: > > On Fri, 2010-07-30 at 08:07 -0400, Jon Smirl wrote: > > > On Fri, Jul 30, 2010 at 8:02 AM, Jon Smirl <jonsmirl@xxxxxxxxx> wrote: > > > > On Fri, Jul 30, 2010 at 7:54 AM, Maxim Levitsky <maximlevitsky@xxxxxxxxx> wrote: > > > > > > > > > > > + pll_freq = (ene_hw_read_reg(dev, ENE_PLLFRH) << 4) + > > > > + (ene_hw_read_reg(dev, ENE_PLLFRL) >> 2); > > > > > > > > > > I can understand the shift of the high bits, but that shift of the low > > > bits is unlikely. A manual would tell us if it is right. > > > > > This shift is correct (according to datasheet, which contains mostly > > useless info, but it does dociment this reg briefly.) > > The KB3700 series datasheet indicates that the value from ENE_PLLFRL > should be shifted by >> 4 bits, not by >> 2. Of course, the KB3700 > isn't the exact same chip. You are right about that, thanks! Best regards, Maxim Levitsky -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
