On 12/07/2022 02:02, Laurent Pinchart wrote: > The Image Sensing Interface (ISI) combines image processing pipelines > with DMA engines to process and capture frames originating from a > variety of sources. The inputs to the ISI go through Pixel Link > interfaces, and their number and nature is SoC-dependent. They cover > both capture interfaces (MIPI CSI-2 RX, HDMI RX) and memory inputs. > > Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > --- > Changes since v1: > > - Fix compatible string checks in conditional schema > - Fix interrupts property handling > --- > .../bindings/media/nxp,imx8-isi.yaml | 148 ++++++++++++++++++ > 1 file changed, 148 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml > new file mode 100644 > index 000000000000..390dfa03026b > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml > @@ -0,0 +1,148 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX8 Image Sensing Interface > + > +maintainers: > + - Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > + > +description: | > + The Image Sensing Interface (ISI) combines image processing pipelines with > + DMA engines to process and capture frames originating from a variety of > + sources. The inputs to the ISI go through Pixel Link interfaces, and their > + number and nature is SoC-dependent. They cover both capture interfaces (MIPI > + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. > + > +properties: > + compatible: > + enum: > + - fsl,imx8mn-isi > + - fsl,imx8mp-isi > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: The AXI clock > + - description: The APB clock > + # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified > + # as well, in case some SoCs have the ability to control them separately. > + # This may be the case of the i.MX8[DQ]X(P) > + > + clock-names: > + items: > + - const: axi > + - const: apb > + > + fsl,blk-ctrl: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + A phandle referencing the block control that contains the CSIS to ISI > + gasket. > + > + interrupts: true Need generic constraints - min/maxItems. > + > + power-domains: true Ditto. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + description: | > + Ports represent the Pixel Link inputs to the ISI. Their number and > + assignment are model-dependent. Each port shall have a single endpoint. > + > + patternProperties: > + "^port@[0-9]$": > + $ref: /schemas/graph.yaml#/properties/port > + unevaluatedProperties: false > + > + unevaluatedProperties: false At least one port is always required? > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - fsl,blk-ctrl > + - ports > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx8mn-isi > + then: > + properties: > + interrupts: > + maxItems: 1 > + ports: > + properties: > + port@0: > + description: MIPI CSI-2 RX > + required: > + - port@0 > + > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx8mp-isi > + then: > + properties: > + interrupts: > + maxItems: 2 You need to describe the items. Best regards, Krzysztof
