Hi Paul,
Thank you for the patch.
On Wed, Jun 15, 2022 at 04:11:23AM +0900, Paul Elder wrote:
> The ISP version in the i.MX8MP has a set of registers currently not
> handled by the driver for output size configuration. Add a feature flag
> to determine if the ISP requires this, and set the registers based on
> that.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> Signed-off-by: Paul Elder <paul.elder@xxxxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c | 8 ++++++++
> drivers/media/platform/rockchip/rkisp1/rkisp1-common.h | 1 +
> drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c | 3 ++-
> drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h | 9 +++++++++
> 4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> index 9edaa95fa44c..35cec263c563 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> @@ -420,6 +420,14 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
> rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
> rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
>
> + if (rkisp1->info->features & RKISP1_FEATURE_MAIN_STRIDE) {
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_LLENGTH, pixm->width);
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_WIDTH, pixm->width);
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_HEIGHT, pixm->height);
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_SIZE,
> + pixm->width * pixm->height);
> + }
> +
> rkisp1_irq_frame_end_enable(cap);
>
> /* set uv swapping for semiplanar formats */
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> index e4f422bed09a..96657e55a5b0 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
> @@ -112,6 +112,7 @@ enum rkisp1_feature {
> RKISP1_FEATURE_MIPI_CSI2 = BIT(0),
> RKISP1_FEATURE_DUAL_CROP = BIT(1),
> RKISP1_FEATURE_RSZ_CROP = BIT(2),
> + RKISP1_FEATURE_MAIN_STRIDE = BIT(3),
> };
>
> /*
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> index 5abe33f5fed4..d68a805e8b6b 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
> @@ -505,7 +505,8 @@ static const struct rkisp1_info imx8mp_isp_info = {
> .isrs = imx8mp_isp_isrs,
> .isr_size = ARRAY_SIZE(imx8mp_isp_isrs),
> .isp_ver = IMX8MP_V10,
> - .features = RKISP1_FEATURE_RSZ_CROP,
> + .features = RKISP1_FEATURE_RSZ_CROP
> + | RKISP1_FEATURE_MAIN_STRIDE,
> };
>
> static const struct of_device_id rkisp1_of_match[] = {
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 1fc54ab22b6d..5c2195019723 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -1013,6 +1013,15 @@
> #define RKISP1_CIF_MI_SP_CB_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000140)
> #define RKISP1_CIF_MI_SP_CR_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000144)
> #define RKISP1_CIF_MI_XTD_FORMAT_CTRL (RKISP1_CIF_MI_BASE + 0x00000148)
> +#define RKISP1_CIF_MI_MP_HANDSHAKE_0 (RKISP1_CIF_MI_BASE + 0x0000014C)
> +#define RKISP1_CIF_MI_MP_Y_LLENGTH (RKISP1_CIF_MI_BASE + 0x00000150)
> +#define RKISP1_CIF_MI_MP_Y_SLICE_OFFSET (RKISP1_CIF_MI_BASE + 0x00000154)
> +#define RKISP1_CIF_MI_MP_C_SLICE_OFFSET (RKISP1_CIF_MI_BASE + 0x00000158)
> +#define RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT (RKISP1_CIF_MI_BASE + 0x0000015C)
> +#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE (RKISP1_CIF_MI_BASE + 0x00000160)
> +#define RKISP1_CIF_MI_MP_Y_PIC_WIDTH (RKISP1_CIF_MI_BASE + 0x00000164)
> +#define RKISP1_CIF_MI_MP_Y_PIC_HEIGHT (RKISP1_CIF_MI_BASE + 0x00000168)
> +#define RKISP1_CIF_MI_MP_Y_PIC_SIZE (RKISP1_CIF_MI_BASE + 0x0000016C)
>
> #define RKISP1_CIF_SMIA_BASE 0x00001A00
> #define RKISP1_CIF_SMIA_CTRL (RKISP1_CIF_SMIA_BASE + 0x00000000)
--
Regards,
Laurent Pinchart
