On Thu, Mar 31, 2022 at 09:55:10AM +0000, Nas Chung wrote: > From: Dafna Hirschfeld <dafna.hirschfeld@xxxxxxxxxxxxx> > > Add a TODO file listing all that is need for destaging. > > Signed-off-by: Robert Beckett <bob.beckett@xxxxxxxxxxxxx> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@xxxxxxxxxxxxx> > --- > drivers/staging/media/wave5/TODO | 64 ++++++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > create mode 100644 drivers/staging/media/wave5/TODO > > diff --git a/drivers/staging/media/wave5/TODO b/drivers/staging/media/wave5/TODO > new file mode 100644 > index 000000000000..425ed42a234c > --- /dev/null > +++ b/drivers/staging/media/wave5/TODO > @@ -0,0 +1,64 @@ > +* Test on real silicon once available > + > + This driver has so far been tested on pre-silicon FPGA and on the beta BeagleV > + board which uses the StarFive JH7100 beta SoC. > + > + Testing on FPGA shows it working fine, though the FPGA uses polled interrupts > + and copied buffers between the host and it's on board RAM. > + > + Testing on BeagleV shows buffer corruption that is currently attributed to a > + known silicon issue in the SoC that makes the cache coherent interconnect not > + so coherent. > + This can likely be solved when the riscv non-coherent dma support lands and > + provide optional v4l2 non-contiguous allocator, though it remains to be seen > + whether support non-coherent use cases will be useful in real world hw. > + > + Until we can test and resolve any issues on final silicon (due 2H 2021) > + this driver should remain in staging. Then why not just wait? Why merge this now? What is the benifit of us taking this code at this point in time for hardware that is no one has as it is not even created? thanks, greg k-h
