The PLL configuration defined here sets 72MHz (which is correct), not
80MHz. Correct the comment.
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx>
Signed-off-by: Daniel Scally <djrscally@xxxxxxxxx>
---
drivers/media/i2c/ov8865.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c
index 7626c8608f8f..8e3f8a554452 100644
--- a/drivers/media/i2c/ov8865.c
+++ b/drivers/media/i2c/ov8865.c
@@ -713,7 +713,7 @@ static const struct ov8865_pll2_config ov8865_pll2_config_native = {
/*
* EXTCLK = 24 MHz
* DAC_CLK = 360 MHz
- * SCLK = 80 MHz
+ * SCLK = 72 MHz
*/
static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
--
2.25.1
