Hello Dave, thank you for your verbose explanation. I think I understand a lot more now about those sensors. I'm using an IMX327 as well, but there doesn't seem to be a huge difference. On Montag, 20 Sept 2021 at 12:27 +0100, Dave Stevenson > It has two clock paths - one driving the pixel array, and one driving > the MIPI core. There is a FIFO between the two, so they can run at > different rates. > > My conclusion is that the pixel array always runs at the same pixel > rate, whether 1080p, 720p, or cropped - 148.5MPix/s. Certainly that > is > the result needed for vblank and hblank controls to work correctly in > computing frame rate. The datasheet again contains fixed register > settings for 25, 30, 50, 60, 100, and 120fps by changing HMAX > (register 0x301c/d), but they are all just linearly scaled values of > each other, so it maps cleanly onto V4L2_CID_HBLANK. VMAX is fixed > for > 1080p and 720p modes, so maps to V4L2_CID_VBLANK. Given that there are fixed numbers for 1080p/720p for VMAX and for 25,30,50,60 fps for HMAX shouldn't those controls be read-only? What's the benefit of being writable in [1]? > The MIPI PHY then runs at a link frequency sufficient to convey the > desired pixels: > - 3564 Mbit/s across 4 lanes for 1080p100/120 10bpp > - 1782 Mbit/s split across 2 or 4 lanes for 1080p or window cropped > modes up to 60fps, 10 or 12bpp. > - 1188 Mbit/s split across 2 or 4 lanes for 720p up to 60fps, 10 or > 12bpp > This is controlled predominantly by INCKSEL1 & 2 (registers > 0x305c/d). > I verified the actual link frequencies used on a scope, and they are > as described. > 1782Mbit/s is sufficient for 1920x1080@60fps 12bpp. Cropping or 10bpp > just increases the per line blanking period on the CSI2 interface. Is there actual blanking on CSI2 interface, as in inserting "dummy" pixels in a row and dummy lines? Given that the spec is not available freely it's hard to understand what's actually happening on the interface. Given that the link frequency is fixed (in this case depending on window mode, input clock and number of lanes) I was wondering what's happening when the payload length changes (e.g. switching bpp or cropping). > AFAICT you could just always run at the 1782 Mbit/s rate with > slightly > increased idle time on the CSI2 bus for the 720p mode, but that isn't > the way Sony have specified it. > > There is a further register to halve the link frequency again for max > 25/30fps modes (0x3405), although doing so has limited benefit (it'd > increase rolling shutter effects as it would increase the temporal > difference between each line). > > I hope that makes things a little clearer. Indeed the current driver > is slightly wrong, but only in relation to pixel rate, not link > frequency. Thanks for confirmation. I meanwhile found the table providing the link frequencies. I assume now that my current problem regarding settle time is somewhere else. I can currently only assume the escape clock is not correct, but there is pretty much no documentation at all on that topic. Thanks and best regards Alexander [1] https://github.com/raspberrypi/linux/commits/rpi-5.10.y/drivers/media/i2c/imx290.c -- Mit freundlichen Grüßen i.A. Alexander Stein Entwicklung Standort Chemnitz Tel. +49 371 433151-0, Fax +49 371 433151-22 Zwickauer Straße 173, 09116 Chemnitz mailto: Alexander.Stein@xxxxxxxxxxxx TQ-Systems GmbH Mühlstraße 2, Gut Delling, 82229 Seefeld Amtsgericht München, HRB 105018 Sitz der Gesellschaft: Seefeld Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider www.tq-group.com
