On 23/07/2021 08:44, Paul Kocialkowski wrote:
> Hi,
>
> On Thu 22 Jul 21, 21:33, Daniel Scally wrote:
>> The PLL configuration defined here sets 72MHz (which is correct), not
>> 80MHz. Correct the comment.
> This is:
>
> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx>
>
> Thanks,
Thank you :)
>
> Paul
>
>> Signed-off-by: Daniel Scally <djrscally@xxxxxxxxx>
>> ---
>> drivers/media/i2c/ov8865.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c
>> index fe60cda3dea7..2ef146e7e7ef 100644
>> --- a/drivers/media/i2c/ov8865.c
>> +++ b/drivers/media/i2c/ov8865.c
>> @@ -713,7 +713,7 @@ static const struct ov8865_pll2_config ov8865_pll2_config_native = {
>> /*
>> * EXTCLK = 24 MHz
>> * DAC_CLK = 360 MHz
>> - * SCLK = 80 MHz
>> + * SCLK = 72 MHz
>> */
>>
>> static const struct ov8865_pll2_config ov8865_pll2_config_binning = {
>> --
>> 2.25.1
>>
