> -----Original Message----- > From: Rob Herring [mailto:robh@xxxxxxxxxx] > Sent: Thursday, June 17, 2021 8:00 AM > To: Ming Qian <ming.qian@xxxxxxx> > Cc: mchehab@xxxxxxxxxx; shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; > hverkuil-cisco@xxxxxxxxx; kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; > dl-linux-imx <linux-imx@xxxxxxx>; Aisheng Dong <aisheng.dong@xxxxxxx>; > linux-media@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Subject: [EXT] Re: [PATCH v2 01/13] dt-bindings: media: imx8q: add imx video > codec bindings > > Caution: EXT Email > > On Mon, Jun 07, 2021 at 04:42:48PM +0800, Ming Qian wrote: > > Add devicetree binding documentation for IMX8Q Video Processing Unit > > IP > > > > Signed-off-by: Ming Qian <ming.qian@xxxxxxx> > > Signed-off-by: Shijie Qin <shijie.qin@xxxxxxx> > > Signed-off-by: Zhou Peng <eagle.zhou@xxxxxxx> > > --- > > .../bindings/media/nxp,imx8q-vpu.yaml | 198 > ++++++++++++++++++ > > 1 file changed, 198 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > > b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > > new file mode 100644 > > index 000000000000..058ca69c107a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > > @@ -0,0 +1,198 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > + > > +%YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Fmedia%2Fnxp%2Cimx8q-vpu.yaml%23&data > =04%7C > > > +01%7Cming.qian%40nxp.com%7Cb8af894b4dd946c3b96108d93122e833%7 > C686ea1d > > > +3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637594848261515925%7CUnk > nown%7CTW > > > +FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > VCI > > > +6Mn0%3D%7C1000&sdata=FYRPH5nh6SysbLJ0bkKy%2Bv1QhNciUh4ijp > bNqAJCGN > > +8%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cmin > g.qian > > > +%40nxp.com%7Cb8af894b4dd946c3b96108d93122e833%7C686ea1d3bc2b > 4c6fa92cd > > > +99c5c301635%7C0%7C0%7C637594848261525925%7CUnknown%7CTWFp > bGZsb3d8eyJW > > > +IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C > 1000 > > > +&sdata=6O4zADjEKA0Mvfchy%2FNVzGEKMfdoYUa%2FoHQ9VEHqXaU% > 3D&res > > +erved=0 > > + > > +title: NXP i.MX8Q video encode and decode accelerators > > + > > +maintainers: > > + - Ming Qian <ming.qian@xxxxxxx> > > + - Shijie Qin <shijie.qin@xxxxxxx> > > + > > +description: |- > > + The Amphion MXC video encoder(Windsor) and decoder(Malone) > > +accelerators present > > + on NXP i.MX8Q SoCs. > > + > > +allOf: > > + - $ref: /schemas/simple-bus.yaml# > > This is not a 'simple-bus'. A simple bus doesn't have power-domains, > memory-region, or mailbox. > > simple-mfd maybe, but looks like there's dependencies here so you should > trigger probing yourself. I will modify the driver and this document according to your suggestion > > + > > +properties: > > + $nodename: > > + pattern: "^vpu-bus@[0-9a-f]+$" > > + > > + compatible: > > + contains: > > No, must be exact. > > > + items: > > + - enum: > > + - nxp,imx8qm-vpu > > + - nxp,imx8qxp-vpu > > + > > + reg: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + memory-region: > > + description: > > + Phandle to a node describing reserved memory used by VPU. > > + (see bindings/reserved-memory/reserved-memory.txt) > > + > > + mailbox: > > This needs to be a pattern looking at the example. > > > + description: > > + Each vpu encoder or decoder correspond a MU, which used for > communication > > + between driver and firmware. Implement via mailbox on driver. > > + (see bindings/mailbox/fsl,mu.yaml) > > Do a $ref to the file. > > > + > > +patternProperties: > > + "^vpu_[en, de]coder@[0-9a-f]+$": > > (en|de) > > > + type: object > > + description: > > + Each core correspond a decoder or encoder, need to configure them > > + separately. NXP i.MX8QM SoC has one decoder and two encoder, > i.MX8QXP SoC > > + has one decoder and one encoder. > > + > > + properties: > > + compatible: > > + oneOf: > > + - const: nxp,imx8q-vpu-decoder > > + - const: nxp,imx8q-vpu-encoder > > + > > + reg: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + mbox-names: > > + items: > > + - const: tx0 > > + - const: tx1 > > + - const: rx > > + > > + mboxes: > > + description: > > + List of phandle of 2 MU channels for tx, 1 MU channel for rx. > > How many? (maxItems: 1 or an 'items' list needed) > > > + boot-region: > > + description: > > + Phandle to a node describing reserved memory used by > firmware > > + loading. > > + > > + rpc-region: > > + description: > > + Phandle to a node describing reserved memory used by RPC > shared > > + memory between firmware and driver. > > + > > + print-offset: > > + description: > > + The memory offset from RPC address, used by reserve firmware > log. > > These need vendor prefix and type ref. > > > + > > + id: > > + description: Index of vpu core. > > Nope. We don't do indexes. > > > + > > + required: > > + - compatible > > + - reg > > + - power-domains > > + - mbox-names > > + - mboxes > > + - boot-region > > + - rpc-region > > + - print-offset > > + - id > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - power-domains > > + - memory-region > > + > > +additionalProperties: true > > + > > +examples: > > + # Device node example for i.MX8QM platform: > > + - | > > + #include <dt-bindings/firmware/imx/rsrc.h> > > + > > + vpu: vpu-bus@2c000000 { > > + compatible = "nxp,imx8qm-vpu", "simple-bus"; > > + ranges = <0x2c000000 0x2c000000 0x2000000>; > > + reg = <0x2c000000 0x1000000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + power-domains = <&pd IMX_SC_R_VPU>; > > + memory-region = <&vpu_reserved>; > > + > > + mu_m0: mailbox@2d000000 { > > + compatible = "fsl,imx6sx-mu"; > > + reg = <0x2d000000 0x20000>; > > + interrupts = <0 472 4>; > > + #mbox-cells = <2>; > > + power-domains = <&pd IMX_SC_R_VPU_MU_0>; > > + }; > > + > > + mu1_m0: mailbox@2d020000 { > > + compatible = "fsl,imx6sx-mu"; > > + reg = <0x2d020000 0x20000>; > > + interrupts = <0 473 4>; > > + #mbox-cells = <2>; > > + power-domains = <&pd IMX_SC_R_VPU_MU_1>; > > + }; > > + > > + mu2_m0: mailbox@2d040000 { > > + compatible = "fsl,imx6sx-mu"; > > + reg = <0x2d040000 0x20000>; > > + interrupts = <0 474 4>; > > + #mbox-cells = <2>; > > + power-domains = <&pd IMX_SC_R_VPU_MU_2>; > > + }; > > + > > + vpu_core0: vpu_decoder@2d080000 { > > + compatible = "nxp,imx8q-vpu-decoder"; > > + reg = <0x2d080000 0x10000>; > > + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; > > + mbox-names = "tx0", "tx1", "rx"; > > + mboxes = <&mu_m0 0 0 > > + &mu_m0 0 1 > > + &mu_m0 1 0>; > > + boot-region = <&decoder_boot>; > > + rpc-region = <&decoder_rpc>; > > + print-offset = <0x180000>; > > + id = <0>; > > + }; > > + > > + vpu_core1: vpu_encoder@2d090000 { > > + compatible = "nxp,imx8q-vpu-encoder"; > > + reg = <0x2d090000 0x10000>; > > + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; > > + mbox-names = "tx0", "tx1", "rx"; > > + mboxes = <&mu1_m0 0 0 > > + &mu1_m0 0 1 > > + &mu1_m0 1 0>; > > + boot-region = <&encoder1_boot>; > > + rpc-region = <&encoder1_rpc>; > > + print-offset = <0x80000>; > > + id = <1>; > > + }; > > + > > + vpu_core2: vpu_encoder@2d0a0000 { > > + reg = <0x2d0a0000 0x10000>; > > + compatible = "nxp,imx8q-vpu-encoder"; > > + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; > > + mbox-names = "tx0", "tx1", "rx"; > > + mboxes = <&mu2_m0 0 0 > > + &mu2_m0 0 1 > > + &mu2_m0 1 0>; > > + boot-region = <&encoder2_boot>; > > + rpc-region = <&encoder2_rpc>; > > + print-offset = <0x80000>; > > + id = <2>; > > + }; > > + }; > > + > > +... > > -- > > 2.31.1
