Hi Nelson and Jose, Thank you for the patch. On Wed, Apr 28, 2021 at 05:25:04PM +0200, Nelson Costa wrote: > Document the bindings for the Synopsys DesignWare HDMI RX. > > Signed-off-by: Jose Abreu <jose.abreu@xxxxxxxxxxxx> > Signed-off-by: Nelson Costa <nelson.costa@xxxxxxxxxxxx> > --- > .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 149 +++++++++++++++++++++ > 1 file changed, 149 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml > > diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml > new file mode 100644 > index 0000000..19c7dd4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml > @@ -0,0 +1,149 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 Device Tree Bindings > + > +maintainers: > + - Jose Abreu <jose.abreu@xxxxxxxxxxxx> > + - Nelson Costa <nelson.costa@xxxxxxxxxxxx> > + > +description: | > + The Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 is an HDMI 2.0 > + Receiver solution that is able to decode video and audio. > + > +properties: > + compatible: > + const: snps,dw-hdmi-rx > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: phandle to the configuration clock > + > + clock-names: > + const: cfg > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + phys: > + maxItems: 1 > + description: phandle for the HDMI RX PHY > + > + phy-names: > + const: hdmi-phy > + > + hdmi-phy@fc: > + type: object > + description: connection point for HDMI PHY > + additionalProperties: false > + > + properties: > + compatible: > + oneOf: > + - const: snps,dw-hdmi-phy-e405 > + - const: snps,dw-hdmi-phy-e406 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: phandle to the configuration clock > + > + clock-names: > + const: cfg > + > + "#phy-cells": > + const: 0 > + > + input-count: > + description: Number of PHY input ports > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [1, 2, 3, 4] > + > + required: > + - compatible > + - reg > + - clocks > + - clock-names > + - "#phy-cells" > + - input-count > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - "#address-cells" > + - "#size-cells" > + - phys > + - phy-names THe bindings should be using OF graph (ports) to model the connection between the HDMI source (usually a connector) and the HDMI RX, and between the HDMI RX and the downstream IP core in the pipeline. > + > +additionalProperties: false > + > +examples: > + - | > + hdmi_rx0: hdmi-rx@0 { > + compatible = "snps,dw-hdmi-rx"; > + reg = <0x0 0x10000>; > + interrupts = <1 2>; > + > + clocks = <&dw_hdmi_refclk>; > + clock-names = "cfg"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + phys = <&hdmi_e405_phy>; > + phy-names = "hdmi-phy"; > + > + hdmi_e405_phy: hdmi-phy@fc { > + compatible = "snps,dw-hdmi-phy-e405"; > + reg = <0xfc>; > + > + clocks = <&dw_hdmi_refclk>; > + clock-names = "cfg"; > + > + #phy-cells = <0>; > + input-count = <4>; > + }; > + }; > + - | > + hdmi_rx1: hdmi-rx@1 { > + compatible = "snps,dw-hdmi-rx"; > + reg = <0x0 0x10000>; > + interrupts = <1 2>; > + > + clocks = <&dw_hdmi_refclk>; > + clock-names = "cfg"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + phys = <&hdmi_e406_phy>; > + phy-names = "hdmi-phy"; > + > + hdmi_e406_phy: hdmi-phy@fc { > + compatible = "snps,dw-hdmi-phy-e406"; > + reg = <0xfc>; > + > + clocks = <&dw_hdmi_refclk>; > + clock-names = "cfg"; > + > + #phy-cells = <0>; > + input-count = <4>; > + }; > + }; -- Regards, Laurent Pinchart
