On Wed, 2021-03-03 at 12:39 +0100, Benjamin Gaignard wrote:
> Add variant to IMX8M to enable G2/HEVC codec.
> Define the capabilities for the hardware up to 3840x2160.
> Retrieve the hardware version at init to distinguish G1 from G2.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx>
> ---
> version 2:
> - remove useless clocks
>
> drivers/staging/media/hantro/hantro_drv.c | 1 +
> drivers/staging/media/hantro/hantro_hw.h | 1 +
> drivers/staging/media/hantro/imx8m_vpu_hw.c | 95 ++++++++++++++++++++-
> 3 files changed, 93 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
> index bc90a52f4d3d..976be7b6ecfb 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -591,6 +591,7 @@ static const struct of_device_id of_hantro_match[] = {
> #endif
> #ifdef CONFIG_VIDEO_HANTRO_IMX8M
> { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
> + { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
> #endif
> { /* sentinel */ }
> };
> diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
> index dade3b0769c1..f61f58da05fe 100644
> --- a/drivers/staging/media/hantro/hantro_hw.h
> +++ b/drivers/staging/media/hantro/hantro_hw.h
> @@ -193,6 +193,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
> extern const struct hantro_variant rk3328_vpu_variant;
> extern const struct hantro_variant rk3288_vpu_variant;
> extern const struct hantro_variant imx8mq_vpu_variant;
> +extern const struct hantro_variant imx8mq_vpu_g2_variant;
>
> extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
>
> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> index d5b4312b9391..46b33531be85 100644
> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> @@ -12,6 +12,7 @@
> #include "hantro.h"
> #include "hantro_jpeg.h"
> #include "hantro_g1_regs.h"
> +#include "hantro_g2_regs.h"
>
> static int imx8mq_runtime_resume(struct hantro_dev *vpu)
> {
> @@ -90,6 +91,26 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
> },
> };
>
> +static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_NV12,
> + .codec_mode = HANTRO_MODE_NONE,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
> + .codec_mode = HANTRO_MODE_HEVC_DEC,
> + .max_depth = 2,
> + .frmsize = {
> + .min_width = 48,
> + .max_width = 3840,
> + .step_width = MB_DIM,
> + .min_height = 48,
> + .max_height = 2160,
> + .step_height = MB_DIM,
> + },
> + },
> +};
> +
> static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
> {
> struct hantro_dev *vpu = dev_id;
> @@ -108,9 +129,42 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
> +{
> + struct hantro_dev *vpu = dev_id;
> + enum vb2_buffer_state state;
> + u32 status;
> +
> + status = vdpu_read(vpu, HEVC_REG_INTERRUPT);
> + state = (status & HEVC_REG_INTERRUPT_DEC_RDY_INT) ?
> + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
> +
> + vdpu_write(vpu, 0, HEVC_REG_INTERRUPT);
> + vdpu_write(vpu, HEVC_REG_CONFIG_DEC_CLK_GATE_E, HEVC_REG_CONFIG);
Is this clock gate enable needed on each interrupt?
> +
> + hantro_irq_done(vpu, state);
> +
> + return IRQ_HANDLED;
> +}
> +
> static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
> {
> - vpu->dec_base = vpu->reg_bases[0];
> + int ret;
> +
> + /* Check variant version */
> + ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
> + if (ret) {
> + dev_err(vpu->dev, "Failed to enable clocks\n");
> + return ret;
> + }
> +
> + /* Make that the device has been reset before read it id */
> + ret = device_reset(vpu->dev);
> + if (ret)
> + dev_err(vpu->dev, "Failed to reset Hantro VPU\n");
> +
> + vpu->core_hw_dec_rev = (vdpu_read(vpu, HEVC_REG_VERSION) >> 16) & 0xffff;
> + clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
>
> return 0;
> }
> @@ -149,17 +203,32 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
> },
> };
>
> +static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
> + [HANTRO_MODE_HEVC_DEC] = {
> + .run = hantro_g2_hevc_dec_run,
> + .reset = imx8mq_vpu_reset,
> + .init = hantro_hevc_dec_init,
> + .exit = hantro_hevc_dec_exit,
> + },
> +};
> +
> /*
> * VPU variants.
> */
>
> static const struct hantro_irq imx8mq_irqs[] = {
> { "g1", imx8m_vpu_g1_irq },
> - { "g2", NULL /* TODO: imx8m_vpu_g2_irq */ },
> };
>
> -static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
> -static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
> +static const struct hantro_irq imx8mq_g2_irqs[] = {
> + { "g2", imx8m_vpu_g2_irq },
> +};
> +
> +static const char * const imx8mq_clk_names[] = { "g1", "bus"};
> +static const char * const imx8mq_reg_names[] = { "g1"};
> +
> +static const char * const imx8mq_g2_clk_names[] = { "g2", "bus"};
> +static const char * const imx8mq_g2_reg_names[] = { "g2"};
>
> const struct hantro_variant imx8mq_vpu_variant = {
> .dec_fmts = imx8m_vpu_dec_fmts,
> @@ -179,3 +248,21 @@ const struct hantro_variant imx8mq_vpu_variant = {
> .reg_names = imx8mq_reg_names,
> .num_regs = ARRAY_SIZE(imx8mq_reg_names)
> };
> +
> +const struct hantro_variant imx8mq_vpu_g2_variant = {
> + .dec_offset = 0x0,
> + .dec_fmts = imx8m_vpu_g2_dec_fmts,
> + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
> + .postproc_fmts = imx8m_vpu_postproc_fmts,
> + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
Is this postproc_fmts correct?
Thanks!
Ezequiel
> + .codec = HANTRO_HEVC_DECODER,
> + .codec_ops = imx8mq_vpu_g2_codec_ops,
> + .init = imx8mq_vpu_hw_init,
> + .runtime_resume = imx8mq_runtime_resume,
> + .irqs = imx8mq_g2_irqs,
> + .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
> + .clk_names = imx8mq_g2_clk_names,
> + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
> + .reg_names = imx8mq_g2_reg_names,
> + .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names),
> +};
