Hi Fabio, On Tue, Jan 05, 2021 at 02:45:40PM -0300, Fabio Estevam wrote: > On Tue, Jan 5, 2021 at 12:31 PM Laurent Pinchart wrote: > > > > Hello, > > > > This large patch series has been sitting in my tree for way too long. I > > haven't posted it yet as I'm running into an issue on my test hardware > > that I can't prove is not a regression from this series, but the > > pressure has grown and the patches are better on the list for review. > > > > There's really not much to detail in the cover letter as there are > > "just" fixes and cleanups I developed while bringing up camera support > > for an i.MX7D platform, and later on an i.MX8MM that shares the same > > MIPI-CSI2 and CSI IP cores (with some differences). > > > > The issue I've noticed is that the CSI writes two images consecutively > > to the same buffer, overwritting memory after the end of the buffer. I > > believe this bug to already be present in mainline, but I can't prove it > > as my sensor won't work without some of the patches in this series. The > > problem could also be sensor-specific. > > > > Rui, would you be able to test this on your i.MX7 hardware to make sure > > there's no regression ? > > Thanks for your series. > > I tested it on a imx6ul-evk board. Thank you. > There is a build error introduced by patch 74/75. I fixed it like this: > > --- a/drivers/staging/media/imx/imx7-mipi-csis.c > +++ b/drivers/staging/media/imx/imx7-mipi-csis.c > @@ -193,6 +193,8 @@ > #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) > #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) > > +/* Debug Control register */ > +#define MIPI_CSIS_DBG_CTRL 0x20 > /* Non-image packet data buffers */ > #define MIPI_CSIS_PKTDATA_ODD 0x2000 > #define MIPI_CSIS_PKTDATA_EVEN 0x3000 Oops. I have a debug patch in my branch on top of the series that adds the macro, that's why I haven't noticed compilation broke. Sorry about that. > Then I applied my patch and Rui's to fix the imx6ul regression as per > the other thread we have been discussing, but I was not able to > capture: Would you be able to bisect this ? > # gst-launch-1.0 -v v4l2src device=/dev/video1 ! v4l2convert ! fbdevsink > Setting pipeline to PAUSED ... > Pipeline is live and does not need PREROLL ... > Pipeline is PREROLLED ... > Setting pipeline to PLAYING ... > New clock: GstSystemClock > /GstPipeline:pipeline0/GstV4l2Src:v4l2src0.GstPad:src: caps = > video/x-raw, format=(string)BGRx, width=(int)3840, height=(int)2160, > framerate=(fraction)120/1, interlace-mode=(string)progressive, > colorimetr > y=(string)1:1:5:1 > /GstPipeline:pipeline0/v4l2convert:v4l2convert0.GstPad:src: caps = > video/x-raw, format=(string)BGRx, width=(int)3840, height=(int)2160, > framerate=(fraction)120/1, interlace-mode=(string)progressive, color > imetry=(string)1:1:5:1 > /GstPipeline:pipeline0/GstFBDEVSink:fbdevsink0.GstPad:sink: caps = > video/x-raw, format=(string)BGRx, width=(int)3840, height=(int)2160, > framerate=(fraction)120/1, interlace-mode=(string)progressive, color > imetry=(string)1:1:5:1 > /GstPipeline:pipeline0/v4l2convert:v4l2convert0.GstPad:sink: caps = > video/x-raw, format=(string)BGRx, width=(int)3840, height=(int)2160, > framerate=(fraction)120/1, interlace-mode=(string)progressive, colo > rimetry=(string)1:1:5:1 > [ 32.783736] cma: cma_alloc: alloc failed, req-size: 8100 pages, ret: -12 > [ 32.791332] imx7-csi 21c4000.csi: dma_alloc_coherent of size 33177600 failed > ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Failed > to allocate required memory. > Additional debug info: > ../sys/v4l2/gstv4l2src.c(659): gst_v4l2src_decide_allocation (): > /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: > Buffer pool activation failed > Execution ended after 0:00:00.214658125 > Setting pipeline to NULL ... > Freeing pipeline ... > > As shown above the dimensions and framerate are incorrectly reported > as: width=(int)3840, height=(int)2160, framerate=(fraction)120/1 > > Previously it was: > > # gst-launch-1.0 -v v4l2src device=/dev/video1 ! v4l2convert ! fbdevsink > Setting pipeline to PAUSED ... > Pipeline is live and does not need PREROLL ... > Pipeline is PREROLLED ... > Setting pipeline to PLAYING ... > New clock: GstSystemClock > /GstPipeline:pipeline0/GstV4l2Src:v4l2src0.GstPad:src: caps = > video/x-raw, format=(string)UYVY, width=(int)320, height=(int)240, > framerate=(fraction)30000/1001, interlace-mode=(string)progressive, > colorim > etry=(string)1:4:7:1 > /GstPipeline:pipeline0/v4l2convert:v4l2convert0.GstPad:src: caps = > video/x-raw, format=(string)BGRx, width=(int)320, height=(int)240, > framerate=(fraction)30000/1001, interlace-mode=(string)progressive > /GstPipeline:pipeline0/GstFBDEVSink:fbdevsink0.GstPad:sink: caps = > video/x-raw, format=(string)BGRx, width=(int)320, height=(int)240, > framerate=(fraction)30000/1001, interlace-mode=(string)progressive > /GstPipeline:pipeline0/v4l2convert:v4l2convert0.GstPad:sink: caps = > video/x-raw, format=(string)UYVY, width=(int)320, height=(int)240, > framerate=(fraction)30000/1001, interlace-mode=(string)progressive, c > olorimetry=(string)1:4:7:1 -- Regards, Laurent Pinchart
