Hi Rob, On Wed, Dec 02, 2020 at 05:13:01PM -0700, Rob Herring wrote: > Convert video-interfaces.txt to DT schema. As it contains a mixture of > device level and endpoint properties, split it up into 2 schemas. > > Binding schemas will need to reference both the graph.yaml and > video-interfaces.yaml schemas. The exact schema depends on how many > ports and endpoints for the binding. A single port with a single > endpoint looks similar to this: > > port: > $ref: /schemas/graph.yaml#/$defs/port-base > > properties: > endpoint: > $ref: video-interfaces.yaml# > unevaluatedProperties: false > > properties: > bus-width: > enum: [ 8, 10, 12, 16 ] > > pclk-sample: true > hsync-active: true > vsync-active: true > > required: > - bus-width > > additionalProperties: false > > Cc: Guennadi Liakhovetski <g.liakhovetski@xxxxxx> > Cc: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx> > Cc: Jacopo Mondi <jacopo@xxxxxxxxxx> > Signed-off-by: Rob Herring <robh@xxxxxxxxxx> > --- > I need acks for dual licensing from the listed maintainers. Thanks for doing the conversion. I'm fine with the license change made by this patch on my contributions. Therefore, Acked-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx> But please also see my comments below. ... > + data-lanes: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 The spec, I believe, specifies maximum of four lanes, but there are implementations that have eight lanes. So I'd use 8 as the maximum instead. > + items: > + # Assume up to 4 data and 1 clock lane > + maximum: 4 > + description: > + An array of physical data lane indexes. Position of an entry determines > + the logical lane number, while the value of an entry indicates physical > + lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;", > + assuming the clock lane is on hardware lane 0. If the hardware does not > + support lane reordering, monotonically incremented values shall be used > + from 0 or 1 onwards, depending on whether or not there is also a clock > + lane. This property is valid for serial busses only (e.g. MIPI CSI-2). > + > + clock-lanes: > + $ref: /schemas/types.yaml#/definitions/uint32 > + # Assume up to 4 data and 1 clock lane > + maximum: 4 There are always zero or one clock lanes, depending on the bus-type. I think we could better document this but I think it should be separate from this patch. > + description: > + Physical clock lane index. Position of an entry determines > + the logical lane number, while the value of an entry indicates physical > + lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which > + places the clock lane on hardware lane 0. This property is valid for > + serial busses only (e.g. MIPI CSI-2). -- Kind regards, Sakari Ailus
