Hi Mauro,
This set adds support for additional CCS PLL features which effectively
allows supporting modern devices from mid-range and up.
I have one more set to post to the list, but I guess that may need to wait
for 5.12. Also, feel free to postpone this until 5.12 if needed.
Please pull.
The following changes since commit 63288c829b1a5991d8f8c15cab596108ed206ba6:
media: pixfmt-compressed.rst: fix 'bullet' formatting (2020-12-03 12:27:34 +0100)
are available in the Git repository at:
git://linuxtv.org/sailus/media_tree.git tags/ccs-v4-pll-cphy-2-signed
for you to fetch changes up to 13c167095b90f5260774a59798e1c7c05d0d82d7:
ccs: Add support for obtaining C-PHY configuration from firmware (2020-12-03 15:54:50 +0200)
----------------------------------------------------------------
CCS PLL feature support improvements
----------------------------------------------------------------
Sakari Ailus (38):
ccs-pll: Don't use div_u64 to divide a 32-bit number
ccs-pll: Split limits and PLL configuration into front and back parts
ccs-pll: Use correct VT divisor for calculating VT SYS divisor
ccs-pll: End search if there are no better values available
ccs-pll: Remove parallel bus support
ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
ccs-pll: Move the flags field down, away from 8-bit fields
ccs-pll: Document the structs in the header as well as the function
ccs-pll: Use the BIT macro
ccs-pll: Begin calculation from OP system clock frequency
ccs-pll: Fix condition for pre-PLL divider lower bound
ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
ccs-pll: Fix comment on check against maximum PLL multiplier
ccs-pll: Fix check for PLL multiplier upper bound
ccs-pll: Use explicit 32-bit unsigned type
ccs-pll: Add support for lane speed model
ccs: Add support for lane speed model
ccs-pll: Add support for decoupled OP domain calculation
ccs-pll: Add support for extended input PLL clock divider
ccs-pll: Support two cycles per pixel on OP domain
ccs-pll: Add support flexible OP PLL pixel clock divider
ccs-pll: Add sanity checks
ccs-pll: Add C-PHY support
ccs-pll: Split off VT subtree calculation
ccs-pll: Check for derating and overrating, support non-derating sensors
ccs-pll: Better separate OP and VT sub-tree calculation
ccs-pll: Print relevant information on PLL tree
ccs-pll: Rework bounds checks
ccs-pll: Make VT divisors 16-bit
ccs-pll: Fix VT post-PLL divisor calculation
ccs-pll: Separate VT divisor limit calculation from the rest
ccs-pll: Add trivial dual PLL support
ccs: Dual PLL support
ccs-pll: Add support for DDR OP system and pixel clocks
ccs: Add support for DDR OP SYS and OP PIX clocks
ccs: Print written register values
ccs-pll: Print pixel rates
ccs: Add support for obtaining C-PHY configuration from firmware
drivers/media/i2c/ccs-pll.c | 986 +++++++++++++++++++++++----------
drivers/media/i2c/ccs-pll.h | 177 ++++--
drivers/media/i2c/ccs/ccs-core.c | 161 ++++--
drivers/media/i2c/ccs/ccs-quirk.c | 5 +-
drivers/media/i2c/ccs/ccs-reg-access.c | 4 +
5 files changed, 974 insertions(+), 359 deletions(-)
--
Sakari Ailus
