Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include
support for C-PHY.
Signed-off-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx>
---
drivers/media/i2c/ccs-pll.c | 2 +-
drivers/media/i2c/ccs-pll.h | 3 ++-
drivers/media/i2c/ccs/ccs-core.c | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index da97a2b91717..c6435ed0597e 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -430,7 +430,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->binning_vertical);
switch (pll->bus_type) {
- case CCS_PLL_BUS_TYPE_CSI2:
+ case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 578c9272688a..d06a80c4fc52 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -13,7 +13,8 @@
#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define CCS_PLL_BUS_TYPE_CSI2 0x00
+#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
+#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 00fb8edb8fc2..591953cec6ec 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3201,7 +3201,7 @@ static int ccs_probe(struct i2c_client *client)
sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
- sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2;
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
--
2.27.0
