The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx> --- drivers/media/i2c/ccs-pll.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 0e474ca65712..c4230c082078 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -204,8 +204,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", more_mul_max); /* Ensure we won't go above max_pll_multiplier. */ - more_mul_max = min(more_mul_max, - DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul)); + more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", more_mul_max); -- 2.27.0
