The parallel bus PLL calculation has no users. Remove it.
Signed-off-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx>
---
drivers/media/i2c/ccs-pll.c | 5 -----
drivers/media/i2c/ccs-pll.h | 14 ++++----------
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 7ee1af198972..61ace70852e0 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -435,11 +435,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
- case CCS_PLL_BUS_TYPE_PARALLEL:
- op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
- / DIV_ROUND_UP(pll->bits_per_pixel,
- pll->parallel.bus_width);
- break;
default:
return -EINVAL;
}
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 03b1d8d11423..578c9272688a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -13,8 +13,7 @@
#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define CCS_PLL_BUS_TYPE_CSI2 0x00
-#define CCS_PLL_BUS_TYPE_PARALLEL 0x01
+#define CCS_PLL_BUS_TYPE_CSI2 0x00
/* op pix clock is for all lanes in total normally */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
@@ -37,14 +36,9 @@ struct ccs_pll_branch_bk {
struct ccs_pll {
/* input values */
uint8_t bus_type;
- union {
- struct {
- uint8_t lanes;
- } csi2;
- struct {
- uint8_t bus_width;
- } parallel;
- };
+ struct {
+ uint8_t lanes;
+ } csi2;
unsigned long flags;
uint8_t binning_horizontal;
uint8_t binning_vertical;
--
2.27.0
