Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
On 2020-07-22 16:23, Christian König wrote:
Am 22.07.20 um 16:07 schrieb Daniel Vetter:
On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
<thomas_os@xxxxxxxxxxxx> wrote:
On 2020-07-22 14:41, Daniel Vetter wrote:
I'm pretty sure there's more bugs, I just haven't heard from them
yet.
Also due to the opt-in nature of dma-fence we can limit the scope of
what we fix fairly naturally, just don't put them where no one cares
:-) Of course that also hides general locking issues in dma_fence
signalling code, but well *shrug*.
Hmm, yes. Another potential big problem would be drivers that want to
use gpu page faults in the dma-fence critical sections with the
batch-based programming model.
Yeah that's a massive can of worms. But luckily there's no such driver
merged in upstream, so hopefully we can think about all the
constraints and how to best annotate&enforce this before we land any
code and have big regrets.
Do you want a bad news? I once made a prototype for that when Vega10
came out.
But we abandoned this approach for the the batch based approach
because of the horrible performance.
In context of the previous discussion I'd consider the fact that it's
not performant in the batch-based model good news :)
Well the Vega10 had such a horrible page fault performance because it
was the first generation which enabled it.
Later hardware versions are much better, but we just didn't push for
this feature on them any more.
But yeah, now you mentioned it we did discuss this locking problem on
tons of team calls as well.
Our solution at that time was to just not allow waiting if we do any
allocation in the page fault handler. But this is of course not
practical for a production environment.
Christian.
Thomas
KFD is going to see that, but this is only with user queues and no
dma_fence involved whatsoever.
Christian.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
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