On Fri, Jun 19, 2020 at 8:58 AM Jason Gunthorpe <jgg@xxxxxxxx> wrote: > > On Thu, Jun 18, 2020 at 05:00:51PM +0200, Daniel Vetter wrote: > > On Wed, Jun 17, 2020 at 12:28:35PM -0300, Jason Gunthorpe wrote: > > > On Wed, Jun 17, 2020 at 08:48:50AM +0200, Daniel Vetter wrote: > > > > > > > Now my understanding for rdma is that if you don't have hw page fault > > > > support, > > > > > > The RDMA ODP feature is restartable HW page faulting just like nouveau > > > has. The classical MR feature doesn't have this. Only mlx5 HW supports > > > ODP today. > > > > > > > It's only gpus (I think) which are in this awkward in-between spot > > > > where dynamic memory management really is much wanted, but the hw > > > > kinda sucks. Aside, about 10+ years ago we had a similar problem with > > > > gpu hw, but for security: Many gpu didn't have any kinds of page > > > > tables to isolate different clients from each another. drivers/gpu > > > > fixed this by parsing&validating what userspace submitted to make sure > > > > it's only every accessing its own buffers. Most gpus have become > > > > reasonable nowadays and do have proper per-process pagetables (gpu > > > > process, not the pasid stuff), but even today there's still some of > > > > the old model left in some of the smallest SoC. > > > > > > But I still don't understand why a dma fence is needed inside the GPU > > > driver itself in the notifier. > > > > > > Surely the GPU driver can block and release the notifier directly from > > > its own command processing channel? > > > > > > Why does this fence and all it entails need to leak out across > > > drivers? > > > > So 10 years ago we had this world of every gpu driver is its own bucket, > > nothing leaks out to the world. But the world had a different idea how > > gpus where supposed to work, with stuff like: > > Sure, I understand DMA fence, but why does a *notifier* need it? > > The job of the notifier is to guarentee that the device it is > connected to is not doing DMA before it returns. > > That just means you need to prove that device is done with the buffer. > > As I've understood GPU that means you need to show that the commands > associated with the buffer have completed. This is all local stuff > within the driver, right? Why use fence (other than it already exists) Because that's the end-of-dma thing. And it's cross-driver for the above reasons, e.g. - device A renders some stuff. Userspace gets dma_fence A out of that (well sync_file or one of the other uapi interfaces, but you get the idea) - userspace (across process or just different driver) issues more rendering for device B, which depends upon the rendering done on device A. So dma_fence A is an dependency and will block this dma operation. Userspace (and the kernel) gets dma_fence B out of this - because unfortunate reasons, the same rendering on device B also needs a userptr buffer, which means that dma_fence B is also the one that the mmu_range_notifier needs to wait on before it can tell core mm that it can go ahead and release those pages - unhappiness ensues, because now the mmu notifier from device B can get hung up on the dma operation device A is doing If you want to avoid this either a) have less shitty hw (not an option, gpus are gpus, it is slowly getting better though) or b) force userspace to stall before handing over to next device (about as uncool) or c) just pin all the memory always, who cares (also rather unpopular, gpus tend to use all the memory they can get). I guess the thing with gpus is that dma operations aren't like read/writes for pretty much everything else, but essentially compute contexts (usually implemented as ringbuffers where you stream stuff into) with cross everything dependencies. This even holds within a single gpu, since pretty much all modern gpus have multiple different engines special on different things. And yup that's directly exposed to userspace, for vulkan and other low-level gpu apis even directly to applications. So dma operation for gpu isn't just "done when the read/write finishes", but pulls in an entire chain of dependencies and ordering that needs to happen before it can even start. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
