On 4/25/20 4:13 PM, Dmitry Osipenko wrote:
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24.04.2020 06:55, Sowjanya Komatineni пишет:
+static int __maybe_unused vi_runtime_resume(struct device *dev)
+{
+ struct tegra_vi *vi = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regulator_enable(vi->vdd);
+ if (ret) {
+ dev_err(dev, "failed to enable VDD supply: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_set_rate(vi->clk, vi->soc->vi_max_clk_hz);
+ if (ret) {
+ dev_err(dev, "failed to set vi clock rate: %d\n", ret);
+ goto disable_vdd;
+ }
Isn't setting clock rate using assigned-clocks in a device-tree enough?
Could you please clarify why this vi_max_clk_hz is needed?
Max clock rate with sensor support will be 998Mhz.
Later when sensor support is added, based on TPG or Sensor mode clock
rate will be set here