Re: [PATCH v3 3/6] media: staging: rkisp1: cap: change the logic for writing to uv swap register

[Dafna Hirschfeld <dafna.hirschfeld@xxxxxxxxxxxxx>]

On 4/8/20 2:10 PM, Laurent Pinchart wrote:
> Hi Dafna,
>
> Thank you for the patch.
>
> On Wed, Apr 08, 2020 at 01:48:19PM +0200, Dafna Hirschfeld wrote:
> > The register RKISP1_CIF_MI_XTD_FORMAT_CTRL is currently written
> > with "on" only if the u,v streams need to be swapped. This patch
> > also write to it with "off" if they don't need to be swapped.
> >
> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@xxxxxxxxxxxxx>
>
> I think you can squash this with 1/6 and 2/6.
Hi, as Helen already commented, since it is a combination of
cleanups and bug fixes, I think it is better to keep them separated.

Thanks,
Dafna
> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
>
> > ---
> >   drivers/staging/media/rkisp1/rkisp1-capture.c | 21 ++++++++++---------
> >   1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/staging/media/rkisp1/rkisp1-capture.c b/drivers/staging/media/rkisp1/rkisp1-capture.c
> > index 5d0e489505f0..4830083c33fd 100644
> > --- a/drivers/staging/media/rkisp1/rkisp1-capture.c
> > +++ b/drivers/staging/media/rkisp1/rkisp1-capture.c
> > @@ -383,12 +383,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
> >   		     cap->config->mi.cr_size_init);
> >   
> >   	rkisp1_irq_frame_end_enable(cap);
> > -	if (cap->pix.cfg->uv_swap) {
> > -		reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> > -
> > +	reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> > +	if (cap->pix.cfg->uv_swap)
> >   		reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
> > -		rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> > -	}
> > +	else
> > +		reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
> > +	rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> >   
> >   	rkisp1_mi_config_ctrl(cap);
> >   
> > @@ -406,7 +406,7 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> >   {
> >   	const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
> >   	struct rkisp1_device *rkisp1 = cap->rkisp1;
> > -	u32 mi_ctrl;
> > +	u32 mi_ctrl, reg;
> >   
> >   	rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
> >   		     cap->config->mi.y_size_init);
> > @@ -420,12 +420,13 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> >   	rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH);
> >   
> >   	rkisp1_irq_frame_end_enable(cap);
> > -	if (cap->pix.cfg->uv_swap) {
> > -		u32 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> >   
> > +	reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> > +	if (cap->pix.cfg->uv_swap)
> >   		reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
> > -		rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> > -	}
> > +	else
> > +		reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
> > +	rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
> >   
> >   	rkisp1_mi_config_ctrl(cap);
> >