On 20/03/2020 00:53, Benoit Parrot wrote:
Tomi,
Thanks for the patch.
On 3/19/20 2:50 AM, Tomi Valkeinen wrote:
The stop-state timeout needs to be over 100us as per CSI spec. With the
CAL fclk of 266 MHZ on DRA76, with the current value the driver uses,
the timeout is 24us. Too small timeout will cause failure to enable the
streaming.
Also, the fclk can be different on other SoCs, as is the case with AM65x
where the fclk is 250 MHz.
This patch fixes the timeout by calculating it correctly based on the
fclk rate.
Isn't this in relation to the clock sourcing the PHY module which is fixed
at 96Mhz (LVDSRX_96M_GFCLK)?
It's not clearly said in the docs. In register descs, it's "L3 cycles", in the content it's
"functional clock cycles" (without specifying which func clock).
As far as I see, this timeout is part of the CAL, not the PHY, so I think it's the CAL functional clock.
Tomi
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