On 3/13/20 12:41 PM, Tomi Valkeinen wrote:
> Sometimes waiting for ComplexIO resetdone timeouts.
This sentence is hard to read. You probably mean:
Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'.
Regards,
Hans
Testing shows that
> sometimes we need to wait more than what the current code does. It is
> not clear how long this wait can be, but it is based on how quickly the
> sensor provides a valid clock, and how quickly CAL syncs to it.
>
> Change the code to make it more obvious how long we'll wait, and set a
> wider range for usleep_range. Increase the timeout to 750ms.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
> ---
> drivers/media/platform/ti-vpe/cal.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
> index 319312770eea..929f9b3ca4f9 100644
> --- a/drivers/media/platform/ti-vpe/cal.c
> +++ b/drivers/media/platform/ti-vpe/cal.c
> @@ -824,20 +824,21 @@ static void csi2_phy_init(struct cal_ctx *ctx)
>
> static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
> {
> - int i;
> + unsigned long timeout;
>
> - for (i = 0; i < 250; i++) {
> + timeout = jiffies + msecs_to_jiffies(750);
> + while (time_before(jiffies, timeout)) {
> if (reg_read_field(ctx->dev,
> CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
> CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
> break;
> - usleep_range(1000, 1100);
> + usleep_range(500, 5000);
> }
> - ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n",
> +
> + ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done\n",
> ctx->csi2_port,
> - reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i,
> - (i >= 250) ? "(timeout)" : "");
> + reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
>
> if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
> CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
>
