Am Mittwoch, 26. Februar 2020, 13:24:53 CET schrieb Johan Jonker:
> Hi Boris,
>
> Dtsi nodes are sort on address.
> The vdec node is now inserted between:
>
> vdec_mmu: iommu @ff660480
> vdec : video-codec @ff660000
> iep_mmu : iommu @ff670800
>
> This should be:
>
> vpu_mmu : iommu @ff650800
> vdec : video-codec @ff660000
> vdec_mmu: iommu @ff660480
>
Simple things like this I can (and do) fix when applying.
The interesting question would be, did patches 1-5 get applied yet?
As I only remember seing Hans' mail from v5, but didn't get any
applied mail for v6 so far.
Heiko
> > From: Boris Brezillon <boris.brezillon at collabora.com>
> >
> > RK3399 has a Video decoder, define the node in the dtsi. We also add
> > the missing power-domain in mmu node and enable the block.
> >
> > Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
> > Signed-off-by: Ezequiel Garcia <ezequiel at collabora.com>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > index 33cc21fcf4c1..a07f857df12f 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > @@ -1285,8 +1285,20 @@ vdec_mmu: iommu at ff660480 {
> > interrupt-names = "vdec_mmu";
> > clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
> > clock-names = "aclk", "iface";
> > + power-domains = <&power RK3399_PD_VDU>;
> > #iommu-cells = <0>;
> > - status = "disabled";
> > + };
> > +
> > + vdec: video-codec at ff660000 {
> > + compatible = "rockchip,rk3399-vdec";
> > + reg = <0x0 0xff660000 0x0 0x400>;
> > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
> > + interrupt-names = "vdpu";
> > + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
> > + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
> > + clock-names = "axi", "ahb", "cabac", "core";
> > + power-domains = <&power RK3399_PD_VDU>;
> > + iommus = <&vdec_mmu>;
> > };
> >
> > iep_mmu: iommu at ff670800 {
>
>
>
>
