Re: 14-bit pixel/media bus formats for i.MX8QM/QXP CSI

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Hello Sakari,

sorry for the late reply.

Am 01/27/20 um 12:46 schrieb Sakari Ailus:
> On Mon, Jan 27, 2020 at 12:26:20PM +0100, Daniel Glöckner wrote:
>> Looking at the driver from NXP we can probably rule out that the driver will be
>> used with anything else than NXP hardware. Half of the register accesses in that
>> driver go to additional logic specific to the i.MX8 (CSR registers) and there is
> 
> What do those registers do, roughly?

Enable signals between the ISI and the CSI controller, change sync polarity,
provide PHY status bits, settings for interlaced mode, power management, etc.

>> placed it into drivers/media/platform/imx8/.
> 
> Should I assume this CSI-2 receiver will have its own compatible string
> specific to these two SoCs?

It is fsl,mxc-mipi-csi2.

And they wrote a second driver used on other SoCs (i.MX8MQ) that, according to
its first commit message, should eventually be merged with the first driver.
Its compatible string is simply fsl,mxc-mipi-csi2_yav. That driver accesses
just a single GPR register which contains a subset of the bits found in the
CSR registers of the i.MX8QXP.

Best regards,

  Daniel

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