On Mon, Dec 16, 2019 at 12:59:16AM +0800, Chen-Yu Tsai wrote: > From: Chen-Yu Tsai <wens@xxxxxxxx> > > The A10/A20 Allwinner SoCs have two camera sensor interface blocks, > named CSI0 and CSI1. The two have the same register layouts with > slightly different features: > > - CSI0 has an image signal processor (ISP); CSI1 doesn't > > - CSI0 can support up to four separate channels under CCIR656; > CSI1 can only support one > > - CSI0 can support up to 16-bit wide bus with YUV422; > CSI1 can support up to 24-bit wide bus with YUV444 > > For now the driver doesn't support wide busses, nor CCIR656. So the > only relevant difference is whether a clock needs to be taken and > enabled for the ISP. > > Add structs to record the differences, tie them to the compatible > strings, and deal with the ISP clock. Support for the new CSI1 > hardware block is added as well. > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> Acked-by: Maxime Ripard <mripard@xxxxxxxxxx> Thanks! Maxime
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