Re: [PATCH v9 2/4] media: staging: phy-rockchip-dphy: add Rockchip MIPI Synopsys DPHY driver

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Hi Helen,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on next-20191108]
[cannot apply to v5.4-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Helen-Koike/Rockchip-ISP-Driver/20191109-020448
base:   git://linuxtv.org/media_tree.git master
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 7.4.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.4.0 make.cross ARCH=mips 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

   In file included from arch/mips/include/asm/div64.h:12:0,
                    from include/linux/kernel.h:18,
                    from include/linux/clk.h:13,
                    from drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:11:
   drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c: In function 'rk_dphy_rx_stream_on':
   include/asm-generic/div64.h:226:28: warning: comparison of distinct pointer types lacks a cast
     (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
                               ^
>> drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:201:2: note: in expansion of macro 'do_div'
     do_div(data_rate_mbps, 1000 * 1000);
     ^~~~~~
   In file included from include/linux/err.h:5:0,
                    from include/linux/clk.h:12,
                    from drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:11:
   include/asm-generic/div64.h:239:25: warning: right shift count >= width of type [-Wshift-count-overflow]
     } else if (likely(((n) >> 32) == 0)) {  \
                            ^
   include/linux/compiler.h:77:40: note: in definition of macro 'likely'
    # define likely(x) __builtin_expect(!!(x), 1)
                                           ^
>> drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:201:2: note: in expansion of macro 'do_div'
     do_div(data_rate_mbps, 1000 * 1000);
     ^~~~~~
   In file included from arch/mips/include/asm/div64.h:12:0,
                    from include/linux/kernel.h:18,
                    from include/linux/clk.h:13,
                    from drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:11:
   include/asm-generic/div64.h:243:22: error: passing argument 1 of '__div64_32' from incompatible pointer type [-Werror=incompatible-pointer-types]
      __rem = __div64_32(&(n), __base); \
                         ^
>> drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c:201:2: note: in expansion of macro 'do_div'
     do_div(data_rate_mbps, 1000 * 1000);
     ^~~~~~
   include/asm-generic/div64.h:217:17: note: expected 'uint64_t * {aka long long unsigned int *}' but argument is of type 'unsigned int *'
    extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
                    ^~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/do_div +201 drivers/staging//media/phy-rockchip-dphy/phy-rockchip-dphy.c

  > 11	#include <linux/clk.h>
    12	#include <linux/io.h>
    13	#include <linux/mfd/syscon.h>
    14	#include <linux/module.h>
    15	#include <linux/of.h>
    16	#include <linux/of_device.h>
    17	#include <linux/phy/phy.h>
    18	#include <linux/phy/phy-mipi-dphy.h>
    19	#include <linux/platform_device.h>
    20	#include <linux/regmap.h>
    21	
    22	#define RK3399_GRF_SOC_CON9	0x6224
    23	#define RK3399_GRF_SOC_CON21	0x6254
    24	#define RK3399_GRF_SOC_CON22	0x6258
    25	#define RK3399_GRF_SOC_CON23	0x625c
    26	#define RK3399_GRF_SOC_CON24	0x6260
    27	#define RK3399_GRF_SOC_CON25	0x6264
    28	#define RK3399_GRF_SOC_STATUS1	0xe2a4
    29	
    30	#define CLOCK_LANE_HS_RX_CONTROL		0x34
    31	#define LANE0_HS_RX_CONTROL			0x44
    32	#define LANE1_HS_RX_CONTROL			0x54
    33	#define LANE2_HS_RX_CONTROL			0x84
    34	#define LANE3_HS_RX_CONTROL			0x94
    35	#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL	0x75
    36	
    37	#define MAX_DPHY_CLK 8
    38	
    39	#define PHY_TESTEN_ADDR			(1 << 16)
    40	#define PHY_TESTEN_DATA			(0 << 16)
    41	#define PHY_TESTCLK			(1 << 1)
    42	#define PHY_TESTCLR			(1 << 0)
    43	#define THS_SETTLE_COUNTER_THRESHOLD	0x04
    44	
    45	#define GRF_SOC_CON12                           0x0274
    46	
    47	#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK   BIT(20)
    48	#define GRF_EDP_REF_CLK_SEL_INTER               BIT(4)
    49	
    50	#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK           BIT(21)
    51	#define GRF_EDP_PHY_SIDDQ_ON                    0
    52	#define GRF_EDP_PHY_SIDDQ_OFF                   BIT(5)
    53	
    54	struct hsfreq_range {
    55		u16 range_h;
    56		u8 cfg_bit;
    57	};
    58	
    59	static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
    60		{   89, 0x00 }, {   99, 0x10 }, {  109, 0x20 }, {  129, 0x01 },
    61		{  139, 0x11 }, {  149, 0x21 }, {  169, 0x02 }, {  179, 0x12 },
    62		{  199, 0x22 }, {  219, 0x03 }, {  239, 0x13 }, {  249, 0x23 },
    63		{  269, 0x04 }, {  299, 0x14 }, {  329, 0x05 }, {  359, 0x15 },
    64		{  399, 0x25 }, {  449, 0x06 }, {  499, 0x16 }, {  549, 0x07 },
    65		{  599, 0x17 }, {  649, 0x08 }, {  699, 0x18 }, {  749, 0x09 },
    66		{  799, 0x19 }, {  849, 0x29 }, {  899, 0x39 }, {  949, 0x0a },
    67		{  999, 0x1a }, { 1049, 0x2a }, { 1099, 0x3a }, { 1149, 0x0b },
    68		{ 1199, 0x1b }, { 1249, 0x2b }, { 1299, 0x3b }, { 1349, 0x0c },
    69		{ 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c }
    70	 };
    71	
    72	static const char * const rk3399_mipidphy_clks[] = {
    73		"dphy-ref",
    74		"dphy-cfg",
    75		"grf",
    76	};
    77	
    78	enum dphy_reg_id {
    79		GRF_DPHY_RX0_TURNDISABLE = 0,
    80		GRF_DPHY_RX0_FORCERXMODE,
    81		GRF_DPHY_RX0_FORCETXSTOPMODE,
    82		GRF_DPHY_RX0_ENABLE,
    83		GRF_DPHY_RX0_TESTCLR,
    84		GRF_DPHY_RX0_TESTCLK,
    85		GRF_DPHY_RX0_TESTEN,
    86		GRF_DPHY_RX0_TESTDIN,
    87		GRF_DPHY_RX0_TURNREQUEST,
    88		GRF_DPHY_RX0_TESTDOUT,
    89		GRF_DPHY_TX0_TURNDISABLE,
    90		GRF_DPHY_TX0_FORCERXMODE,
    91		GRF_DPHY_TX0_FORCETXSTOPMODE,
    92		GRF_DPHY_TX0_TURNREQUEST,
    93		GRF_DPHY_TX1RX1_TURNDISABLE,
    94		GRF_DPHY_TX1RX1_FORCERXMODE,
    95		GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
    96		GRF_DPHY_TX1RX1_ENABLE,
    97		GRF_DPHY_TX1RX1_MASTERSLAVEZ,
    98		GRF_DPHY_TX1RX1_BASEDIR,
    99		GRF_DPHY_TX1RX1_ENABLECLK,
   100		GRF_DPHY_TX1RX1_TURNREQUEST,
   101		GRF_DPHY_RX1_SRC_SEL,
   102		/* rk3288 only */
   103		GRF_CON_DISABLE_ISP,
   104		GRF_CON_ISP_DPHY_SEL,
   105		GRF_DSI_CSI_TESTBUS_SEL,
   106		GRF_DVP_V18SEL,
   107		/* below is for rk3399 only */
   108		GRF_DPHY_RX0_CLK_INV_SEL,
   109		GRF_DPHY_RX1_CLK_INV_SEL,
   110	};
   111	
   112	struct dphy_reg {
   113		u16 offset;
   114		u8 mask;
   115		u8 shift;
   116	};
   117	
   118	#define PHY_REG(_offset, _width, _shift) \
   119		{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
   120	
   121	static const struct dphy_reg rk3399_grf_dphy_regs[] = {
   122		[GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
   123		[GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
   124		[GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
   125		[GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
   126		[GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
   127		[GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
   128		[GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
   129		[GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
   130		[GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
   131		[GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
   132		[GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
   133		[GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
   134		[GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
   135		[GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
   136		[GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
   137		[GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
   138		[GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
   139		[GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
   140		[GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
   141		[GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
   142		[GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
   143		[GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
   144		[GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
   145		[GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
   146		[GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
   147	};
   148	
   149	struct dphy_drv_data {
   150		const char * const *clks;
   151		unsigned int num_clks;
   152		const struct hsfreq_range *hsfreq_ranges;
   153		unsigned int num_hsfreq_ranges;
   154		const struct dphy_reg *regs;
   155	};
   156	
   157	struct rockchip_dphy {
   158		struct device *dev;
   159		struct regmap *grf;
   160		struct clk_bulk_data clks[MAX_DPHY_CLK];
   161	
   162		const struct dphy_drv_data *drv_data;
   163		struct phy_configure_opts_mipi_dphy config;
   164	};
   165	
   166	static inline void rk_dphy_write_grf(struct rockchip_dphy *priv,
   167					     unsigned int index, u8 value)
   168	{
   169		const struct dphy_reg *reg = &priv->drv_data->regs[index];
   170		/* Update high word */
   171		unsigned int val = (value << reg->shift) |
   172				   (reg->mask << (reg->shift + 16));
   173	
   174		WARN_ON(!reg->offset);
   175		regmap_write(priv->grf, reg->offset, val);
   176	}
   177	
   178	static void rk_dphy_write_rx(struct rockchip_dphy *priv,
   179				     u8 test_code, u8 test_data)
   180	{
   181		/*
   182		 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
   183		 * is latched internally as the current test code. Test data is
   184		 * programmed internally by rising edge on TESTCLK.
   185		 */
   186		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
   187		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_code);
   188		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 1);
   189		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 0);
   190		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTEN, 0);
   191		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTDIN, test_data);
   192		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
   193	}
   194	
   195	static void rk_dphy_rx_stream_on(struct rockchip_dphy *priv)
   196	{
   197		const struct dphy_drv_data *drv_data = priv->drv_data;
   198		struct phy_configure_opts_mipi_dphy *config = &priv->config;
   199		unsigned int i, hsfreq = 0, data_rate_mbps = config->hs_clk_rate;
   200	
 > 201		do_div(data_rate_mbps, 1000 * 1000);
   202	
   203		dev_dbg(priv->dev, "%s: lanes %d - data_rate_mbps %u\n",
   204			__func__, config->lanes, data_rate_mbps);
   205	
   206		for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
   207			if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
   208				hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
   209				break;
   210			}
   211		}
   212	
   213		rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
   214		rk_dphy_write_grf(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
   215	
   216		/* Disable lane turn around, which is ignored in receive mode */
   217		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
   218		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
   219	
   220		rk_dphy_write_grf(priv, GRF_DPHY_RX0_ENABLE, GENMASK(config->lanes - 1, 0));
   221	
   222		/* dphy start */
   223		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLK, 1);
   224		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 1);
   225		usleep_range(100, 150);
   226		rk_dphy_write_grf(priv, GRF_DPHY_RX0_TESTCLR, 0);
   227		usleep_range(100, 150);
   228	
   229		/* set clock lane */
   230		/* HS hsfreq_range & lane 0  settle bypass */
   231		rk_dphy_write_rx(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
   232		/* HS RX Control of lane0 */
   233		rk_dphy_write_rx(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
   234		/* HS RX Control of lane1 */
   235		rk_dphy_write_rx(priv, LANE1_HS_RX_CONTROL, hsfreq << 1);
   236		/* HS RX Control of lane2 */
   237		rk_dphy_write_rx(priv, LANE2_HS_RX_CONTROL, hsfreq << 1);
   238		/* HS RX Control of lane3 */
   239		rk_dphy_write_rx(priv, LANE3_HS_RX_CONTROL, hsfreq << 1);
   240		/* HS RX Data Lanes Settle State Time Control */
   241		rk_dphy_write_rx(priv, HS_RX_DATA_LANES_THS_SETTLE_CONTROL,
   242				 THS_SETTLE_COUNTER_THRESHOLD);
   243	
   244		/* Normal operation */
   245		rk_dphy_write_rx(priv, 0x0, 0);
   246	}
   247	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx Intel Corporation

Attachment: .config.gz
Description: application/gzip


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