From: Frederic Chen <frederic.chen@xxxxxxxxxxxx> This patch adds DT binding documentation for the Digital Image Processing (DIP) unit of camera ISP system on Mediatek's SoCs. It depends on the SCP and MDP 3 patch as following: 1. dt-bindings: Add a binding for Mediatek SCP https://patchwork.kernel.org/patch/11027247/ 2. dt-binding: mt8183: Add Mediatek MDP3 dt-bindings https://patchwork.kernel.org/patch/10945603/ Signed-off-by: Frederic Chen <frederic.chen@xxxxxxxxxxxx> --- .../bindings/media/mediatek,mt8183-dip.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt new file mode 100644 index 000000000000..3a0435513089 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-dip.txt @@ -0,0 +1,40 @@ +* Mediatek Digital Image Processor (DIP) + +Digital Image Processor (DIP) unit in Mediatek ISP system is responsible for +image content adjustment according to the tuning parameters. DIP can process +the image form memory buffer and output the processed image to multiple output +buffers. Furthermore, it can support demosaicing and noise reduction on the +images. + +Required properties: +- compatible: "mediatek,mt8183-dip" +- reg: Physical base address and length of the function block register space +- interrupts: interrupt number to the cpu +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,mdp3: should point to the respective mdp block. DIP hardware + connects to MDP and we can get the processed image with both effect of the + two blocks. +- mediatek,larb: must contain the local arbiters in the current SoCs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- mediatek,scp: should point to the scp node since the we use SCP + coprocessor to control DIP hardware +- clocks: must contain the local arbiters 5 (LARB5) and DIP clock +- clock-names: must contain "larb5" and "dip" + +Example: + dip: dip@15022000 { + compatible = "mediatek,mt8183-dip"; + mediatek,larb = <&larb5>; + mediatek,mdp3 = <&mdp_rdma0>; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_IMGI>; + reg = <0 0x15022000 0 0x6000>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_LOW>; + clocks = <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_DIP>; + clock-names = "larb5", + "dip"; + }; -- 2.18.0
