Hi Louis,
On Thu, Jun 06, 2019 at 06:00:32PM +0800, Louis Kuo wrote:
> This patch adds the DT binding documentation for the sensor interface
> module in Mediatek SoCs.
>
> Signed-off-by: Louis Kuo <louis.kuo@xxxxxxxxxxxx>
> ---
> .../devicetree/bindings/media/mediatek-seninf.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.txt b/Documentation/devicetree/bindings/media/mediatek-seninf.txt
> new file mode 100644
> index 0000000..979063a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.txt
> @@ -0,0 +1,31 @@
> +* Mediatek seninf MIPI-CSI2 host driver
Note that DT bindings document the hardware, not the driver implementation.
> +
> +Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support a widely adopted,
Same here; driver apparently refers to software.
Please wrap before or at 80 characters per line.
> +simple, high-speed protocol primarily intended for point-to-point image and video
> +transmission between cameras and host devices.
Could you elaborate the properties of the hardware in a bit more detail,
such as how many ports there are and how many lanes they can support? See
e.g. Documentation/devicetree/bindings/media/ti,omap3isp.txt .
Please also refer to video-interfaces.txt and document the port nodes and
the relevant properties in the endpoint nodes, as in the binding example I
referred to.
> +
> +Required properties:
> + - compatible: "mediatek,mt8183-seninf"
> + - reg: Must contain an entry for each entry in reg-names.
> + - reg-names: Must include the following entries:
> + "base_reg": seninf registers base
> + "rx_reg": Rx analog registers base
> + - interrupts: interrupt number to the cpu.
> + - clocks : clock name from clock manager
> + - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF.
> + It is the clocks of seninf
> +
> +Example:
> + seninf: seninf@1a040000 {
> + compatible = "mediatek,mt8183-seninf";
> + reg = <0 0x1a040000 0 0x8000>,
> + <0 0x11C80000 0 0x6000>;
> + reg-names = "base_reg", "rx_reg";
> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
> + clocks =
> + <&camsys CLK_CAM_SENINF>, <&topckgen CLK_TOP_MUX_SENINF>;
Please wrap before 80 and align the above two lines.
> + clock-names =
> + "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF";
No need to wrap here.
> + }
> +
> --
> 1.9.1
This must be old.
--
Regards,
Sakari Ailus
