Hi Eugen, Thanks for reaching out. > -----Original Message----- > From: Eugen.Hristev@xxxxxxxxxxxxx [mailto:Eugen.Hristev@xxxxxxxxxxxxx] > Sent: Tuesday, March 12, 2019 4:30 PM > To: vishal.sagar@xxxxxxxxxx; Hyun Kwon <hyunk@xxxxxxxxxx>; > laurent.pinchart@xxxxxxxxxxxxxxxx; mchehab@xxxxxxxxxx; > robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; Michal Simek > <michals@xxxxxxxxxx>; linux-media@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; sakari.ailus@xxxxxxxxxxxxxxx; > hans.verkuil@xxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; Dinesh Kumar <dineshk@xxxxxxxxxx>; Sandip Kothari > <sandipk@xxxxxxxxxx> > Subject: Re: [PATCH v6 0/2] Add support for Xilinx CSI2 Receiver Subsystem > > EXTERNAL EMAIL > > On 12.03.2019 06:35, Vishal Sagar wrote: > > Xilinx MIPI CSI-2 Receiver Subsystem > > ------------------------------------ > > > > The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which > > gets the data, an optional I2C, a CSI-2 Receiver which parses the data and > > converts it into AXIS data. > > This stream output maybe connected to a Xilinx Video Format Bridge. > > The maximum number of lanes supported is fixed in the design. > > The number of active lanes can be programmed. > > For e.g. the design may set maximum lanes as 4 but if the camera sensor has > > only 1 lane then the active lanes shall be set as 1. > > > > The pixel format set in design acts as a filter allowing only the selected > > data type or RAW8 data packets. The D-PHY register access can be gated in > > the design. The base address of the DPHY depends on whether the internal > > Xilinx I2C controller is enabled or not in design. > > Hi Vishal, > > Do you also include a driver for the DPHY ? Namely I am interested in > something which can comply to the PHY subsystem specifications, so it > can be referenced by possibly other nodes ? > No the DPHY driver isn't included now as the DPHY register interface can be optionally enabled. But the idea is to add that kind of support in future. > Something like this: > > xilinx_dphy: dphy@40000 { > compatible = "xlnx,dphy"; > > #phy-cells = <0>; > > reg = <0x40000 0x100>; > > }; > > From my understanding your RX system can be referenced as a whole, > without being able to have the PHY as separate node, and creating > references maybe like : > > phys = <&xilinx_dphy>; > True. Currently this is how it is implemented without the phys dt entry. Regards Vishal Sagar > > Thanks, > > Eugen > > > > > > > The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device > > having 2 pads. The sink pad is connected to the MIPI camera sensor and > > output pad is connected to the video node. > > Refer to xlnx,csi2rxss.txt for device tree node details. > > > > This driver helps configure the number of active lanes to be set, setting > > and handling interrupts and IP core enable. It logs the number of events > > occurring according to their type between streaming ON and OFF. > > It generates a v4l2 event for each short packet data received. > > The application can then dequeue this event and get the requisite data > > from the event structure. > > > > It adds new V4L2 controls which are used to get the event counter values > > and reset the subsystem. > > > > The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be > > used for image processing. This data follows the video formats mentioned > > in Xilinx UG934 when the Video Format Bridge is enabled. > > > > v6 > > - 1/2 > > - Added minor comment by Luca > > - Added Reviewed by Rob Herring > > - 2/2 > > - No change > > > > v5 > > - 1/2 > > - Removed the DPHY clock description and dt node. > > - removed bayer pattern as CSI doesn't deal with it. > > - 2/2 > > - removed bayer pattern as CSI doesn't deal with it. > > - add YUV422 10bpc media bus format. > > > > v4 > > - 1/2 > > - Added reviewed by Hyun Kwon > > - 2/2 > > - Removed irq member from core structure > > - Consolidated IP config prints in xcsi2rxss_log_ipconfig() > > - Return -EINVAL in case of invalid ioctl > > - Code formatting > > - Added reviewed by Hyun Kwon > > > > v3 > > - 1/2 > > - removed interrupt parent as suggested by Rob > > - removed dphy clock > > - moved vfb to optional properties > > - Added required and optional port properties section > > - Added endpoint property section > > - 2/2 > > - Fixed comments given by Hyun. > > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver > > - Minor code formatting > > - en_csi_v20 and vfb members removed from struct and made local to dt > parsing > > - lock description updated > > - changed to ratelimited type for all dev prints in irq handler > > - Removed YUV 422 10bpc media format > > > > v2 > > - 1/2 > > - updated the compatible string to latest version supported > > - removed DPHY related parameters > > - added CSI v2.0 related property (including VCX for supporting upto 16 > > virtual channels). > > - modified csi-pxl-format from string to unsigned int type where the value > > is as per the CSI specification > > - Defined port 0 and port 1 as sink and source ports. > > - Removed max-lanes property as suggested by Rob and Sakari > > > > - 2/2 > > - Fixed comments given by Hyun and Sakari. > > - Made all bitmask using BIT() and GENMASK() > > - Removed unused definitions > > - Removed DPHY access. This will be done by separate DPHY PHY driver. > > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra > > virtual channels > > - Fixed the ports as sink and source > > - Now use the v4l2fwnode API to get number of data-lanes > > - Added clock framework support > > - Removed the close() function > > - updated the set format function > > - Support only VFB enabled config > > > > Vishal Sagar (2): > > media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem > > media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver > > > > .../bindings/media/xilinx/xlnx,csi2rxss.txt | 118 ++ > > drivers/media/platform/xilinx/Kconfig | 10 + > > drivers/media/platform/xilinx/Makefile | 1 + > > drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1465 > ++++++++++++++++++++ > > include/uapi/linux/xilinx-v4l2-controls.h | 14 + > > include/uapi/linux/xilinx-v4l2-events.h | 25 + > > 6 files changed, 1633 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt > > create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c > > create mode 100644 include/uapi/linux/xilinx-v4l2-events.h > >
