On Sat, Aug 25, 2018 at 01:32:47PM +0200, Sakari Ailus wrote: > On Fri, Aug 24, 2018 at 02:05:17PM +0200, Helmut Grohne wrote: > > Take for instance MT9M024. The data sheet > > (http://www.mouser.com/ds/2/308/MT9M024-D-606228.pdf) allows deducing > > the following limits: > > > > const struct aptina_pll_limits mt9m024_limits = { > > .ext_clock_min = 6000000, > > .ext_clock_max = 50000000, > > .int_clock_min = 2000000, > > .int_clock_max = 24000000, > > .out_clock_min = 384000000, > > .out_clock_max = 768000000, > > .pix_clock_max = 74250000, > > .n_min = 1, > > .n_max = 63, > > .m_min = 32, > > .m_max = 255, > > .p1_min = 4, > > .p1_max = 16, > > }; > > > > Now if you choose ext_clock and pix_clock maximal within the given > > limits, the existing aptina_pll_calculate gives up. Lowering the > > pix_clock does not help either. Even down to 73 MHz, it is unable to > > find any pll configuration. > > > > The new algorithm finds a solution (n=11, m=98, p1=6) with 7.5 KHz > > error. Incidentally, that solution is close to the one given by the > > vendor tool (n=22, m=196, p1=6). > > These values don't seem valid for 6 MHz --- the frequency after the PLL is > less than 384 MHz. Did you use a different external clock frequency? I wrote that I used the maximal external clock frequency, which is 50 MHz. For that value, the output clock is within the requested bounds. Are you implying that the chosen pll parameters should be valid for all possible external clocks simultaneously? Helmut
