On Tue, Jul 10, 2018 at 4:00 PM, Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> wrote: > From: Maxime Ripard <maxime.ripard@xxxxxxxxxxx> > > This introduces support for the SRAM C1 section, that is controlled by > the system controller. This SRAM area can be muxed either to the CPU > or the Video Engine, that needs this area to store various tables (e.g. > the Huffman VLD decoding tables). > > This only supports devices with the same layout as the A10 (which also > includes the A13, A20, A33 and other SoCs). > > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxx> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxx>
