Hi Samuel, On Wed, Apr 18, 2018 at 04:39:06PM -0700, Samuel Bobrowicz wrote: > I applied your patches, and they are a big improvement for what I am > trying to do, but things still aren't working right on my platform. > > How confident are you that the MIPI mode will work with this version > of the driver? Not too confident. Like I said, I did all my tests on a parallel camera with a scope, so I'm pretty confident for the parallel bus. But I haven't been able to test the MIPI-CSI side of things and tried to deduce it from the datasheet. tl; dr: I might very well be wrong. > I am having issues that I believe are due to incorrect clock > generation. Our engineers did some reverse engineering of the clock > tree themselves, and came up with a slightly different model. I've > captured their model in a spreadsheet here: > https://tinyurl.com/pll-calc . Just modify the register and xclk > values to see the clocks change. Do your tests disagree with this > potential model? At least on the parallel side, it looks fairly similar, so I guess we can come to an agreement :) There's just the SCLK2x divider that is no longer in the path to PCLK but has been replaced with BIT Divider that has the same value, so it should work as well. > I'm not sure which model is more correct, but my tests suggest the > high speed MIPI clock is generated directly off the PLL. This means > the PLL multiplier you are generating in your algorithm is not high > enough to satisfy the bandwidth. If this is the case, MIPI mode will > require a different set of parameters that enable some of the > downstream dividers, so that the PLL multiplier can be higher while > the PCLK value still matches the needed rate calculated from the > resolution. > > Any thoughts on this before I dive in and start tweaking the algorithm > in mipi mode? Like I said, I did that analysis by plugging the camera to a scope and look at the PCLK generated for various combinations. Your analysis seems not too far off for the setup I've tested, so I guess this makes sense. And let me know how it works for MIPI-CSI2 so that I can update the patches :) Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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