Re: [PATCH v4 0/9] vsp1: TLB optimisation and DL caching

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Hi Kieran,

On Fri, Nov 17, 2017 at 4:47 PM, Kieran Bingham
<kieran.bingham+renesas@xxxxxxxxxxxxxxxx> wrote:
> Each display list currently allocates an area of DMA memory to store register
> settings for the VSP1 to process. Each of these allocations adds pressure to
> the IPMMU TLB entries.
>
> We can reduce the pressure by pre-allocating larger areas and dividing the area
> across multiple bodies represented as a pool.
>
> With this reconfiguration of bodies, we can adapt the configuration code to
> separate out constant hardware configuration and cache it for re-use.
>
> --
>
> The patches provided in this series can be found at:
>   git://git.kernel.org/pub/scm/linux/kernel/git/kbingham/rcar.git  tags/vsp1/tlb-optimise/v4

This started to conflict with commit dd286a531461748f ("v4l: vsp1:
Start and stop DRM pipeline independently of planes"), causing build
failures as it changes the signature of vsp1_entity_route_setup(), and
removed several VSP1_ENTITY_PARAMS_* definitions.

After fixing those, it hangs after:
     [drm] No driver support for vblank timestamp query.

So I dropped the above for today's release.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds



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