The existing fixed value of 16 worked for UYVY 720P60 over 2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888 1080P60 needs 6 lanes at 594MHz). It doesn't allow for lower resolutions to work as the FIFO underflows. Using a value of 300 works for all resolutions down to VGA60, and the increase in frame delay is <4usecs for 1080P60 UYVY (2.55usecs for RGB888). Signed-off-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx> --- drivers/media/i2c/tc358743.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index 6b0fd07..7632daf 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -1782,8 +1782,14 @@ static int tc358743_probe_of(struct tc358743_state *state) state->pdata.refclk_hz = clk_get_rate(refclk); state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; state->pdata.enable_hdcp = false; - /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ - state->pdata.fifo_level = 16; + /* + * A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz, + * but is insufficient for lower resolutions. + * A value of 300 allows for resolutions down to VGA60 (and possibly + * lower) to work, whilst still leaving the delay for 1080P60 + * stilll below 4usecs. + */ + state->pdata.fifo_level = 300; /* * The PLL input clock is obtained by dividing refclk by pll_prd. * It must be between 6 MHz and 40 MHz, lower frequency is better. -- 2.7.4
