Hi Maxime, On Mon, Sep 04, 2017 at 03:03:34PM +0200, Maxime Ripard wrote: > The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to > 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on > the hardware implementation. > > It can operate with an external D-PHY, an internal one or no D-PHY at all > in some configurations. > > Acked-by: Rob Herring <robh@xxxxxxxxxx> > Acked-by: Benoit Parrot <bparrot@xxxxxx> > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > --- > .../devicetree/bindings/media/cdns-csi2rx.txt | 98 ++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/cdns-csi2rx.txt Naming this according to the compatible string would make it easier to find. The same pattern is used by a number of existing binding files. Up to you. > > diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt > new file mode 100644 > index 000000000000..2395030d8c72 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt > @@ -0,0 +1,98 @@ > +Cadence MIPI-CSI2 RX controller > +=============================== > + > +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI > +lanes in input, and 4 different pixel streams in output. > + > +Required properties: > + - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible > + - reg: base address and size of the memory mapped region > + - clocks: phandles to the clocks driving the controller > + - clock-names: must contain: > + * sys_clk: main clock > + * p_clk: register bank clock > + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream > + implemented in hardware, between 0 and 3 > + > +Optional properties: > + - phys: phandle to the external D-PHY, phy-names must be provided > + - phy-names: must contain dphy, if the implementation uses an > + external D-PHY > + > +Required subnodes: > + - ports: A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. The > + first port subnode should be the input endpoint, the next ones the > + output, one for each stream supported by the CSI2-RX controller. While I guess the DT compiler won't rearrange the nodes, it'd be better to define the port numbers explicitly, i.e. that input is number 0. > + The ports ID must be the stream output number used in the > + implementation, plus 1. And also that outputs are from 1 to 4. With that, Acked-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx> -- Sakari Ailus e-mail: sakari.ailus@xxxxxx
