Hi Thierry,
W dniu 12.06.2017 o 19:13, Thierry Escande pisze:
From: Abhilash Kesavan <a.kesavan@xxxxxxxxxxx>
This patch resets the encoding and decoding register bits before doing a
soft reset.
Here are my thoughts after consulting the documentation:
Signed-off-by: Tony K Nadackal <tony.kn@xxxxxxxxxxx>
Signed-off-by: Thierry Escande <thierry.escande@xxxxxxxxxxxxx>
---
drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
index a1d823a..9ad8f6d 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c
@@ -21,6 +21,10 @@ void exynos4_jpeg_sw_reset(void __iomem *base)
unsigned int reg;
reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
+ writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE),
+ base + EXYNOS4_JPEG_CNTL_REG);
Indeed, if encoding/decoding "back-to-back", the bits this patch touches
should be reset.
The doc also says, that "Soft reset is asserted to all registers
of JPEG except soft reset bit itself", so, theoretically speaking,
the changes in this patch are redundant. Instead, the doc says,
these bits have to be reset after servicing the interrupt for current image
and before programming the hardware to perform the next en/decoding.
And indeed, the first thing that both ENCODE and DECODE paths
of exynos4_jpeg_device_run() do is calling sw reset.
If, however, you can show that the changes in the patch discussed here
are in fact necessary (that's the very difference between theory and practise...),
I will readily ack it.
Andrzej
