Hi Laurent > > >> Laurent: what do you think about the need for SoC-specific compatible > > >> values for the various IM* blocks? > > > > > > There's no documented IP core version register, but when dumping all > > > configuration registers on H3 and M3-W I noticed that register 0x002c, not > > > documented in the datasheet, reads 0x14060514 on all four IMR instances in > > > H3, and 0x20150505 on both instances in M3-W. > > > > > > This looks like a version register to me. If my assumption is correct, we > > > could do without any SoC-specific compatible string. > > > > I read this assumed version registers on all R-Car SoCs, after writing > > zero to 0xe6150990 (SMSTPCR8). > > > > IMR-X2 on R-Car H2: 0x12072009 > > IMR-LSX2 on R-Car H2: 0x12072009 > > IMR-LSX3 on R-Car V2H: 0x13052617 > > IMR-LX2 on R-Car M2-W: 0x12072009 > > IMR-LX2 on R-Car M2-N: 0x12072009 > > IMR-LX2 on R-Car E2: 0x13091909 > > IMR-LX3 on R-Car V2H: 0x13052617 > > > > Note that several IDs are the same, but you know the type from the > > compatible value. > > > > It would be good to get confirmation from the hardware team that this is > > indeed a version register. > > Thank you for checking. > > Morimoto-san, do you think there are still people alive in the Gen2 hardware > team who could provide the information ? :-) If not, information restricted to > Gen3 would still be useful. Hmm.. I will try to ask to HW team. My assumption is "No answer for no documented register". Thus, we have 5% chance (?) Please wait Best regards --- Kuninori Morimoto
