Igor M. Liplianin wrote:
On 5 June 2009 21:41:46 Simon Kenyon wrote:
Simon Kenyon wrote:
Simon Kenyon wrote:
the picture seems to be breaking up badly
will revert to my version and see if that fixes it
[sorry for the delay. i was away on business]
i've checked and your original code, modified to compile and including
my changes to control the LNB works very well; the patch you posted does
not. i have swapped between the two and rebooted several times to make
sure.
i will do a diff and see what the differences are
regards
--
simon
the main changes seem to be a reworking of the interrupt handling and
some i2c changes
--
simon
How fast is your system?
reasonably fast
it is a dual core AMD64 X2 running at 3.1GHz
/proc/cpuinfo says:
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 107
model name : AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
stepping : 2
cpu MHz : 3100.268
cache size : 512 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm cmp_legacy
svm extapic cr8_legacy 3dnowprefetch
bogomips : 6203.89
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc 100mhzsteps
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 107
model name : AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
stepping : 2
cpu MHz : 3100.268
cache size : 512 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
apicid : 1
initial apicid : 1
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm cmp_legacy
svm extapic cr8_legacy 3dnowprefetch
bogomips : 6203.89
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc 100mhzsteps
--
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