Hello Raphael, Thanks for this patch. I have a question below. On 9/16/19 8:41 PM, Raphael Moreira Zinsly wrote: > Add entries for the new cache geometry values of the auxiliary vectors > that got included in the kernel. > > Signed-off-by: Raphael Moreira Zinsly <rzinsly@xxxxxxxxxxxxxxxxxx> > --- > man3/getauxval.3 | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/man3/getauxval.3 b/man3/getauxval.3 > index 794bc97b5..30f0757b5 100644 > --- a/man3/getauxval.3 > +++ b/man3/getauxval.3 > @@ -123,6 +123,33 @@ The instruction cache block size. > .\" .TP > .\" .BR AT_NOTELF > .TP > +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147 > +.BR AT_L1D_CACHEGEOMETRY > +Geometry of the L1 data cache, that is, line size and number > +of ways. What is "number of ways"? Thanks, Michael > +.TP > +.BR AT_L1D_CACHESIZE > +The L1 data cache size. > +.TP > +.BR AT_L1I_CACHEGEOMETRY > +Geometry of the L1 instruction cache, that is, line size and > +number of ways. > +.TP > +.BR AT_L1I_CACHESIZE > +The L1 instruction cache size. > +.TP > +.BR AT_L2_CACHEGEOMETRY > +Geometry of the L2 cache, that is, line size and number of ways. > +.TP > +.BR AT_L2_CACHESIZE > +The L2 cache size. > +.TP > +.BR AT_L3_CACHEGEOMETRY > +Geometry of the L3 cache, that is, line size and number of ways. > +.TP > +.BR AT_L3_CACHESIZE > +The L3 cache size. > +.TP > .BR AT_PAGESZ > The system page size (the same value returned by > .IR sysconf(_SC_PAGESIZE) ). > -- Michael Kerrisk Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/ Linux/UNIX System Programming Training: http://man7.org/training/
