Am 06.03.2017 20:08, schrieb Mike Frysinger:
> On 06 Mar 2017 12:01, Michael Kerrisk (man-pages) wrote:
>> [Extending the CC for some other input. Changhee Han added the text
>> that you are asking about; Mike F has done a lot of other work on the
>> page. Perhaps they can comment.]
>>
>> On 5 March 2017 at 09:08, Victor Khimenko <khim@xxxxxxxxxx> wrote:
>>> syscall(2) example includes the following snippet which explains how to
>>> call readahead on ARM:
>>>
>>> syscall(SYS_readahead, fd, 0,
>>> (unsigned int) (offset >> 32),
>>> (unsigned int) (offset & 0xFFFFFFFF),
>>> count);
>>>
>>> But ARM EABI specifies that "A double-word sized type is passed in two
>>> consecutive registers (e.g., r0 and r1, or r2 and r3). The content of
>>> the registers is as if the value had been loaded from memory representation
>>> with a single LDM instruction."
>>>
>>> This would imply that arguments are swapped around in the man page, no?
>>
>> So, I'm taking it that you mean the call should look like this:
>>
>> syscall(SYS_readahead, fd, 0,
>> (unsigned int) (offset & 0xFFFFFFFF),
>> (unsigned int) (offset >> 32),
>> count);
>>
>> Is that what you mean?
>>
>>> I've tried to experiement and with ftruncate, at least, it works like
>>> this...
>>
>> Sounds plausible. I'm hoping that Mike or Changhee Han might comment.
>
> it depends on the endianness. the man page shows BE, and Victor's
> suggestion changes it to LE. we probably need to explain that and
> not just swap the args in the example.
> -mike
I think that the point is: "invokes the system call whose assembly language interface"
And a lot of new programmes have no experience with assembler these days. So the example
should go into more details an explain how this is mapped into registers.
e.g. ARM/EABI
syscall(SYS_readahead, // r7
fd, // r0
0, // r1
(unsigned int) (offset >> 32), // r2
(unsigned int) (offset & 0xFFFFFFFF), // r3
count); //r4
Then the next lines make more sense for the reader:
" Since the offset argument is 64 bits, and the first argument (fd) is
passed in r0, the caller must manually split and align the 64-bit value
so that it is passed in the r2/r3 register pair. That means inserting
a dummy value into r1 (the second argument of 0)."
then adding something like pitfalls:
The programmer needs to be aware of the endianess of is cpu. Big Endian CPU will
need to swap arguments.
@khim@xxxxxxxxxx
what do you think ?
re,
wh
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