On 11-Apr-13, at 9:55 PM, Mike Frysinger wrote:
On Sunday 07 April 2013 14:48:42 John David Anglin wrote:
On 7-Apr-13, at 2:39 PM, Mike Frysinger wrote:
just to be clear, the only insn you need is:
ble 0x100(%sr2, %r0);
the kernel docs say sr2 holds the kernel gateway page (so i guess
0x100 is a
known offset into that). the docs don't mention r0 that i can see,
so i'm
guessing it's one of those "always 0" registers ?
Yes. There is also an entry at offset 0xb0 for light-weight-
syscalls. Currently,
this implements an atomic CAS operation used for pthread support.
interesting. sounds like a poor man's vDSO. i'll document this the
new
vdso(7) man page.
Not exactly, the code runs on the gateway page which is in kernel space.
The main reason for doing the operation in kernel space is to prevent
processes from being preempted while executing in the lock region. In
general,
parisc processes are not preempted on the gateway page. There are
some subtleties regarding fault handling.
There is support in glibc and libgcc for these calls. The libgcc
implementation
in linux-atomic.c is very similar to that on arm.
Dave
--
John David Anglin dave.anglin@xxxxxxxx
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