Hi !
On 02/12/2024 10:29, Jean-Michel Hautbois wrote:
This patch series adds support for DMA timers for the M5441x coldfire
family. The aim is to provide finer scheduler resolution and support for
high-resolution timers.
The first patch fixes the clocks and a typo. The second one is the
timers support addition. As there is no device tree, I did not use
TIMER_OF_DECLARE().
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@xxxxxxxxxx>
---
Jean-Michel Hautbois (2):
m68k: coldfire: Use proper clock rate for timers
m68k: m5441x: Add DMA timer support
MAINTAINERS | 6 +
arch/m68k/coldfire/m5441x.c | 20 +--
arch/m68k/include/asm/m5441xsim.h | 18 +++
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/mcf_dma_timer.c | 240 ++++++++++++++++++++++++++++++++++++
6 files changed, 284 insertions(+), 10 deletions(-)
---
base-commit: e3f432391d55ec21274bd16a04659b4a24678535
change-id: 20241202-m5441x_dma_tmr-d969f4cc30a8
Best regards,
Gentle ping, as I don't know if anyone is interested by this patch :-) ?
I think it makes coldfire really better but it certainly has issues !
On my kernel, m54418, I observed a few things.
First, when launching cyclictest I get sometimes a bad irq handle:
[ 720.442175] irq 24, desc: 6b62142b, depth: 1, count: 0, unhandled: 0
[ 720.442329] ->handle_irq(): e4232a91, handle_bad_irq+0x0/0x1e6
[ 720.442498] ->irq_data.chip(): 66a62b77, 0x4183e868
[ 720.442613] ->action(): 00000000
[ 720.442667] unexpected IRQ trap at vector 18
These IRQ numbers are a bit weird, I suppose it is a spurious IRQ, but
not sure ?
Next, cyclictest might experience *very* long delay if the CPU is very
busy and a ping flood burst comes in:
# cyclictest -m -p 98 --secaligned
WARN: stat /dev/cpu_dma_latency failed: No such file or directory
policy: fifo: loadavg: 2.24 1.94 1.03 1/127 252
T: 0 ( 251) P:98 I:1000 C: 53113 Min: 116 Act: 327 Avg: 209 Max:
60353
Any review would be appreciated, at least to know if it is totally off
or not that bad and needs a few fixes ?
Thanks,
JM
