Hi Christoph,
On 9/10/23 22:58, Christoph Hellwig wrote:
On Mon, Oct 09, 2023 at 11:29:12AM +0100, Robin Murphy wrote:
It looks a bit odd that this ends up applying to all of Coldfire, while the
associated cache flush only applies to the M532x platform, which implies
that we'd now be relying on the non-coherent allocation actually being
coherent on other Coldfire platforms.
Would it work to do something like this to make sure dma-direct does the
right thing on such platforms (which presumably don't have caches?), and
then reduce the scope of this FEC hack accordingly, to clean things up even
better?
Probably. Actually Greg comment something along the lines last
time, and mentioned something about just instruction vs instruction
and data cache.
I just elaborated on that point a little in response to Robin's email.
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index b826e9c677b2..1851fa3fe077 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -27,6 +27,7 @@ config COLDFIRE
select CPU_HAS_NO_BITFIELDS
select CPU_HAS_NO_CAS
select CPU_HAS_NO_MULDIV64
+ select DMA_DEFAULT_COHERENT if !MMU && !M523x
Although it would probably make more sense to simply not select
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE and
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU for these platforms and not
build the non-coherent code at all. This should also include
all coldfire platforms with mmu (M54xx/M548x/M5441x). Then
again for many of the coldfire platforms the Kconfig allows
to select CACHE_WRITETHRU/CACHE_COPYBACK which looks related.
Greg, any chance you could help out with the caching modes on
coldfire and legacy m68knommu?
Sure, yep. I am not aware that the legacy 68000 or 68328 had any caches
at all.
The cache modes change a bit through out the various ColdFire family series, but
can be broken down roughly into 2 groups.
1. Version 2 cores (so everything named 52xx). Early members (5206, 5206e, 5272)
had instruction cache only. Later members (5208, 5271/5275, 523x, etc) had
a selectable instruction or data or both cache arrangement. Kconfig lets you
select which you want - the default is instruction cache only.
2. Version 3 and 4 cores (so everything named 53xx and 54xx). They have a unified
instruction and data cache. Data caching can be selected to be write-through
(the default) or write-back.
Some of the version 4 cores also have an MMU.
The M532x hack in the fec driver is to deal with its unified cache, and it is the
only ColdFire version 3 or 4 SoC that has the fec hardware module (thus no others
listed out there). I suspect if you select data cache on the version 2 cores that have
it would break in the fec driver too.
Regards
Greg
