On 2023-10-09 10:51, Geert Uytterhoeven wrote:
Hi Christoph,
CC soc
On Mon, Oct 9, 2023 at 11:43 AM Christoph Hellwig <hch@xxxxxx> wrote:
On Mon, Oct 09, 2023 at 11:34:55AM +0200, Geert Uytterhoeven wrote:
The fix you are referring too is probably commit c1ec4b450ab729e3
("soc: renesas: Make ARCH_R9A07G043 (riscv version) depend
on NONPORTABLE") in next-20231006 and later. It is not yet upstream.
Still, it merely makes ARCH_R9A07G043 (which selects DMA_GLOBAL_POOL)
depend on ARCH_R9A07G043.
RISCV_DMA_NONCOHERENT still selects DMA_DIRECT_REMAP, so both can end
up being enabled.
Ok, so we need to actually fix this properly. Lad, can you respin
the fix to not select DMA_DIRECT_REMAP, for ARCH_R9A07G043?
ARCH_R9A07G043 does not select DMA_DIRECT_REMAP directly,
RISCV_DMA_NONCOHERENT does. And there are other users of
RISCV_DMA_NONCOHERENT (RISCV_ISA_ZICBOM and ERRATA_THEAD_CMO).
Should the selection of DMA_DIRECT_REMAP moved to their users?
No, the selection of DMA_GLOBAL_POOL should be removed from
RISV_DMA_NONCOHERENT and selected directly by ARCH_R9A07G043 (along with
any of the other implied symbols it needs). Or if as suggested this
physical-attribute-remap wackiness is due to show up on more platforms
as well, maybe have a common config for that which selects
DMA_GLOBAL_POOL plus the relevant cache maintenance extensions as an
equivalent to RISCV_DMA_NONCOHERENT, and can itself explicitly depend on
NONPORTABLE for clarity.
Thanks,
Robin.
Note that the fix is already in soc/for-next, so we need coordination
with the soc people.
Gr{oetje,eeting}s,
Geert
